## Speeding up Pipelined Circuits through a Combination of Gate Sizing and Clock Skew Optimization (1995)

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Venue: | Proc. Int'l Conf. on Computer-Aided Design |

Citations: | 12 - 0 self |

### BibTeX

@INPROCEEDINGS{Sathyamurthy95speedingup,

author = {Harsha Sathyamurthy and Sachin S. Sapatnekar and John P. Fishburn},

title = {Speeding up Pipelined Circuits through a Combination of Gate Sizing and Clock Skew Optimization},

booktitle = {Proc. Int'l Conf. on Computer-Aided Design},

year = {1995},

pages = {467--470}

}

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### Abstract

An algorithm for unifying the techniques of gate sizing and clockskew optimization for acyclic pipelines is presented in this paper. In the design of circuits under very tight timing specifications, the area overhead of gate sizing can be considerable. The procedure utilizes the idea of cycle-borrowing using clock skew optimization to relax the stringency of the timing specification on the critical stages of the pipeline. Experimental results verify that cycle-borrowing using sizing+skew results in a better overall area-delay tradeoff than with sizing alone.

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Citation Context ...r programming problem. However, the accuracy of piecewise linear models used in that work is limited, and hence it is desirable to investigate techniques that use the more accurate Elmore delay model =-=[16]-=- directly, as has been done for the sizing problem for combinational circuits in [3{6]. The combined problem of sizing and skew optimization is formulated as: minimize Area subject to xi + d(i; j)+Tse... |

164 |
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Citation Context ...lized in isolation for speeding up circuits; we unify them to arrive at an optimal design. Gate sizing is a well-known technique and several CAD tools have been developed to perform this optimization =-=[1, 2]-=-. Given the circuit topology, the delay of a combinational circuit can be controlled by varying the sizes of transistors in the circuit. In coarse terms, the circuit delay can usually be reduced by in... |

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Citation Context ...of clock signals at the ip- ops (FF's). One approach that has been followed by several researchers is to design the clock distribution network so as to ensure zero clock skew. An alternative approach =-=[3,4]-=- views clock skews as a manageable resource rather than a liability, and manipulates clock skews to advantage by intentionally introducing skews to improve the performance of the circuit. This process... |

90 | An exact solution to the transistor sizing problem for CMOS circuits using convex optimization
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Citation Context ...lized in isolation for speeding up circuits; we unify them to arrive at an optimal design. Gate sizing is a well-known technique and several CAD tools have been developed to perform this optimization =-=[1, 2]-=-. Given the circuit topology, the delay of a combinational circuit can be controlled by varying the sizes of transistors in the circuit. In coarse terms, the circuit delay can usually be reduced by in... |

50 |
An exact zero-skew clock routing algorithm
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Citation Context ...pendent skew variations. Introducing deliberate delays within the clocking network has been a tactic that has long been used by designers [6], and this may be adapted to build xed-skew clock networks =-=[7]-=-. In fact, it is a misconception to believe that zero skew is entirely safe. To see this, consider a shift register consisting of register A whose output is connected to register B with no combination... |

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Citation Context ... di erences in interconnect delays on the clock distribution network of integrated circuits, there is typically a skew between the arrival times of clock signals at the ip- ops (FF's). One approach ( =-=[7, 8]-=- etc.) that has been followed by several researchers is to design the clock distribution network so as to ensure zero clockskew. An alternative approach [9,10] views clockskews as a manageable resourc... |

39 | A graph-theoretic approach to clock skew optimization - Deokar, Sapatnekar - 1994 |

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Citation Context ...n amuck, we introduce the constraint (4). This constraint may easily be incorporated into our solution. Under the Elmore delay model, it can be shown [1] that the gate delays are posynomial functions =-=[9]-=- of the gate sizes. A posynomial function in x can be transformed into a convex function in z using the mapping xi = e z i . Based on this fact, it was pointed out in [3] that the above optimization p... |

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Citation Context ..., in Step 2, the short path constraint violations are resolved by padding the circuit with bu ers as necessary. This paper focuses on the solution of the Step 1, and adaptations of techniques such as =-=[5]-=- may be used to reconcile short path violations. The technique is illustratedson single-phase clocked circuits containing edge-triggered FF's. It was previously thought that it was extremely hard to a... |

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Citation Context ...derably more complex. We will elaborate on this in Section 3. 5s2.3 Is Clock Skew Optimization Safe? Several procedures for building clocking networks for nonzero skew are available in the literature =-=[8, 12]. How-=-ever, a common misconception that persists among circuit designers about changing clock skews is that it is believed to be an \unsafe" optimization, in that a small change in the gate/interconnec... |

5 |
Clock system design
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Citation Context ...rcuit will operate in the presence of unintentional process-dependent skew variations. Introducing deliberate delays within the clocking network has been a tactic that has long been used by designers =-=[6]-=-, and this may be adapted to build xed-skew clock networks [7]. In fact, it is a misconception to believe that zero skew is entirely safe. To see this, consider a shift register consisting of register... |

5 | Gamal. Optimal selection of transistor sizes in digital VLSI circuits - Marple, El - 1987 |

4 |
Performance Optimization of Pipelined Circuits
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(Show Context)
Citation Context ...area-delay tradeo as compared to using sizing alone. 1 Introduction The problem of optimizing acyclic pipelines has attracted considerable interest of late; recent publications on the subject include =-=[1, 2]-=-. This paper presents a method for speeding up acyclic pipelined circuits through a combination of two techniques: gate sizing and clockskew optimization. Each of these techniques has been utilized in... |

2 |
Resynthesis of multi-phase pipelines
- Shenoy, Brayton, et al.
- 1993
(Show Context)
Citation Context ...area-delay tradeo as compared to using sizing alone. 1 Introduction The problem of optimizing acyclic pipelines has attracted considerable interest of late; recent publications on the subject include =-=[1, 2]-=-. This paper presents a method for speeding up acyclic pipelined circuits through a combination of two techniques: gate sizing and clockskew optimization. Each of these techniques has been utilized in... |

2 |
A 250-MHz Skewed-Clock Pipelined Data Buffer
- Heshami, Wooley
- 1996
(Show Context)
Citation Context ...and this may be adapted to build xed-skew clock networks. As a proof of the practicality of this concept, a pipelined data bu er chip using the concept of skewed clocks was designed and fabricated in =-=[14]-=-. In fact, it is a misconception to believe that zero skew is entirely safe. To see this, consider a shift register consisting of register A whose output is connected to register B with no combination... |

1 |
A uni ed algorithm for gate sizing and clock skew optimization to minimize sequential circuit area
- Chuang, Sapatnekar, et al.
- 1993
(Show Context)
Citation Context ...t double-clocking. 3 Formulation of the Problem The combination of clockskew optimization and sizing into a single framework was thoughttobetoointractable a problem to solve [3]. A recent approach in =-=[8]-=- used piecewise linear models to arrive at a solution, setting up the combined problem as an LP. However, the accuracy of such models is limited, and hence it is desirable to investigate techniques th... |