Speeding up Pipelined Circuits through a Combination of Gate Sizing and Clock Skew Optimization

Speeding up Pipelined Circuits through a Combination of Gate Sizing and Clock Skew Optimization (1995)

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by Harsha Sathyamurthy , Sachin S. Sapatnekar , John P. Fishburn

Venue:	Proc. Int'l Conf. on Computer-Aided Design
Citations:	13 - 0 self

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@INPROCEEDINGS{Sathyamurthy95speedingup,
    author = {Harsha Sathyamurthy and Sachin S. Sapatnekar and John P. Fishburn},
    title = {Speeding up Pipelined Circuits through a Combination of Gate Sizing and Clock Skew Optimization},
    booktitle = {Proc. Int'l Conf. on Computer-Aided Design},
    year = {1995},
    pages = {467--470}
}

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Abstract

An algorithm for unifying the techniques of gate sizing and clockskew optimization for acyclic pipelines is presented in this paper. In the design of circuits under very tight timing specifications, the area overhead of gate sizing can be considerable. The procedure utilizes the idea of cycle-borrowing using clock skew optimization to relax the stringency of the timing specification on the critical stages of the pipeline. Experimental results verify that cycle-borrowing using sizing+skew results in a better overall area-delay tradeoff than with sizing alone.

Citations

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