## Advanced unbounded model checking based on aigs, bdd sweeping, and quantifier scheduling

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Venue: | in Proceedings of the Conference on Formal Methods in Computer Aided Design (FMCAD). IEEE Computer Society Press, Nov 2006 |

Citations: | 9 - 5 self |

### BibTeX

@INPROCEEDINGS{Pigorsch_advancedunbounded,

author = {Florian Pigorsch and Christoph Scholl and Stefan Disch},

title = {Advanced unbounded model checking based on aigs, bdd sweeping, and quantifier scheduling},

booktitle = {in Proceedings of the Conference on Formal Methods in Computer Aided Design (FMCAD). IEEE Computer Society Press, Nov 2006},

year = {},

pages = {89--96}

}

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### Abstract

Abstract — In this paper we present a complete method for verifying properties expressed in the temporal logic CTL. In contrast to the majority of verification methods presented in recent years, we support unbounded model checking based on symbolic representations of characteristic functions. Among others, our method is based on an advanced And-Inverter Graph (AIG) implementation, quantifier scheduling, and BDD sweeping. For several examples, our method outperforms BDD based symbolic model checking by orders of magnitude. However, our approach is also able to produce competitive results for cases where BDD are known to perform well. I.

### Citations

1327 |
Symbolic Model Checking
- McMillan
- 1993
(Show Context)
Citation Context ...is a method for verifying these properties [1], [2]. In the early nineties, by introducing symbolic model checking, Burch et al. substantially extended the class of systems which can be verified [3], =-=[4]-=-. In symbolic model checking binary decision diagrams (BDDs) [5] are used both for state set representation and for state traversal. Sets of states are represented by characteristic functions which in... |

735 | Symbolic Model Checking without BDDs
- Biere, Cimatti, et al.
- 1999
(Show Context)
Citation Context ...tate traversal. Sets of states are represented by characteristic functions which in turn are represented by BDDs. However, in the last few years SAT based techniques like Bounded Model Checking (BMC) =-=[6]-=-, [7] have been attracting much interest, since industrial needs ask for methods avoiding the well known memory explosion problem which may occur during symbolic model checking of large circuits. BMC ... |

337 |
The Complexity of Propositional Linear Temporal Logics
- Sistla, Clarke
- 1985
(Show Context)
Citation Context ... cases where BDD are known to perform well. I. INTRODUCTION Given a sequential circuit and properties in some temporal logic like CTL or LTL, model checking is a method for verifying these properties =-=[1]-=-, [2]. In the early nineties, by introducing symbolic model checking, Burch et al. substantially extended the class of systems which can be verified [3], [4]. In symbolic model checking binary decisio... |

329 |
Graph based algorithms for boolean function manipulation
- Bryant
- 1986
(Show Context)
Citation Context ...y nineties, by introducing symbolic model checking, Burch et al. substantially extended the class of systems which can be verified [3], [4]. In symbolic model checking binary decision diagrams (BDDs) =-=[5]-=- are used both for state set representation and for state traversal. Sets of states are represented by characteristic functions which in turn are represented by BDDs. However, in the last few years SA... |

281 |
Automatic Verification of Finite- state Concurrent Systems using Temporal Logic Specifications
- Clarke, Emerson, et al.
- 1986
(Show Context)
Citation Context ...s where BDD are known to perform well. I. INTRODUCTION Given a sequential circuit and properties in some temporal logic like CTL or LTL, model checking is a method for verifying these properties [1], =-=[2]-=-. In the early nineties, by introducing symbolic model checking, Burch et al. substantially extended the class of systems which can be verified [3], [4]. In symbolic model checking binary decision dia... |

281 | Symbolic model checking using sat procedures instead of bdds
- Biere, Cimatti, et al.
- 1999
(Show Context)
Citation Context ...traversal. Sets of states are represented by characteristic functions which in turn are represented by BDDs. However, in the last few years SAT based techniques like Bounded Model Checking (BMC) [6], =-=[7]-=- have been attracting much interest, since industrial needs ask for methods avoiding the well known memory explosion problem which may occur during symbolic model checking of large circuits. BMC appli... |

159 |
Checking safety properties using induction and a SAT-solver
- Sheeran, Singh, et al.
- 2000
(Show Context)
Citation Context ...mplete method for verifying properties expressed in the temporal logic CTL. Our method is 1 Another possibility consists in increasing k up to the length of the longest simple path between two states =-=[8]-=-. Whereas it is easier to determine the length of the longest simple path than to determine the diameter of the system, the longest simple path may be exponentially longer than the diameter. If this i... |

133 | Applying sat methods in unbounded symbolic model checking
- McMillan
- 2002
(Show Context)
Citation Context ... we succeed in limiting the increase in size by several measures including a clever choice of the order of quantifications (‘quantifier scheduling’). Interestingly, in contrast to a widespread belief =-=[16]-=-, [17], [18] our results prove that – for our approach – quantifier elimination by a circuit-based computation of f|x=0 + f|x=1 is not restricted to models with a small number of inputs (which have to... |

89 | Equivalence checking using cuts and heaps
- Kuehlmann, Krohm
- 1997
(Show Context)
Citation Context ...of AIG nodes, whereas unfavorable orders like the order UP shown above lead to an exponential peak size in the number of AIG nodes before the final result 1 is computed. VI. BDD SWEEPING BDD sweeping =-=[20]-=-, [9], [10] is a well-known technique from the domain of combinational equivalence checking (CEC). It builds BDDs for AIG nodes starting at the primary inputs until a certain node limit is reached. Wh... |

79 | Symbolic Reachability Analysis Based on SAT-Solvers
- Abdulla, Bjesse, et al.
- 2000
(Show Context)
Citation Context ...ying sums of sequences of inputs according to the formula registernew = ⌈ registerold 2 ⌉ + input. 9 Note that the barrelshifter example used here is different from the barrelshifter example given in =-=[13]-=-, [14]. The examples in [13], [14] do not contain inputs, and thus, quantification is not needed during the fixed point computation of the model checking procedure (see Section II, equation (2)). We d... |

78 | M.K.: Robust boolean reasoning for equivalence checking and functional property verification
- Kuehlmann, Paruthi, et al.
- 2002
(Show Context)
Citation Context ...ion relation for such a large number of steps will be prohibitive. based on a symbolic representation of sets of states. However, our symbolic representation relies on And-Inverter Graphs (AIGs) [9], =-=[10]-=- instead of BDDs. So far, And-Inverter Graphs have been successfully applied in combinational equivalence checking [9], [10] and in BMC for simplifying representations of transition relations [11]. Ba... |

45 | Combining decision diagrams and SAT procedures for efficient symbolic model checking
- Williams, Biere, et al.
- 2000
(Show Context)
Citation Context ...tations using ‘SAT sweeping’ and functional simulation can be also found in [11]. The most difficult step during model checking using FRAIGs is the elimination of existential quantifiers. As in [13], =-=[14]-=-, [15] existential quantifiers ∃xf are eliminated by replacing them by f|x=0 +f|x=1. Of course, in the worst case the elimination of one quantifier may double the size of the representation. Although ... |

39 | FRAIGs: A unifying representation for logic synthesis and verification
- Mishchenko, Chatterjee, et al.
- 2005
(Show Context)
Citation Context ... 1. In order to obtain as much sharing of subcircuits as possible we make use of a special version of AIGs, the so-called functionally reduced AIGs (FRAIGs) which were introduced by Mishchenko et al. =-=[12]-=- in the context of logic synthesis, technology mapping and combinational equivalence checking. Like general AIGs, FRAIGs still form non-canonical representations of Boolean functions, but they have th... |

34 | Dynamic Transition Relation Simplification for Bounded Property Checking - Kuehlmann |

28 |
SAT-based unbounded symbolic model checking
- Kang, Park
(Show Context)
Citation Context ...tations for state sets by AIG based representations. Other related approaches perform quantifier elimination by using a SAT solver for enumerating all satisfying assignments of a given function [16], =-=[19]-=-. During the enumeration process disjunctions of cubes (or conjunctions of clauses) are collected leading to a two-level representation of the result of the quantification. Characteristic functions fo... |

27 | DAG-aware circuit compression for formal verification
- Bjesse, Boralv
- 2004
(Show Context)
Citation Context ...tainly, our prototype implementation will also profit from the integration of a number of interesting ideas recently developed for optimizing AIG representations such as DAG-aware circuit compression =-=[23]-=-, [24] and advanced rewriting methods [15], [24]. In the future we will investigate whether methods for structural SAT solving [9] will be useful in our context and we will explore whether it sometime... |

23 |
Efficient SAT-based Unbounded Symbolic Model Checking Using Circuit Cofactoring
- Ganai, Gupta, et al.
- 2004
(Show Context)
Citation Context ...in limiting the increase in size by several measures including a clever choice of the order of quantifications (‘quantifier scheduling’). Interestingly, in contrast to a widespread belief [16], [17], =-=[18]-=- our results prove that – for our approach – quantifier elimination by a circuit-based computation of f|x=0 + f|x=1 is not restricted to models with a small number of inputs (which have to be quantifi... |

20 | Equivalence checking combining a structural sat-solver, bdds, and simulation
- Paruthi, Kuehlmann
- 2000
(Show Context)
Citation Context ...ansition relation for such a large number of steps will be prohibitive. based on a symbolic representation of sets of states. However, our symbolic representation relies on And-Inverter Graphs (AIGs) =-=[9]-=-, [10] instead of BDDs. So far, And-Inverter Graphs have been successfully applied in combinational equivalence checking [9], [10] and in BMC for simplifying representations of transition relations [1... |

5 | Circuit based quantification: Back to state set manipulation with unbounded model checking
- Cabodi, Crivellari, et al.
- 2005
(Show Context)
Citation Context ...s using ‘SAT sweeping’ and functional simulation can be also found in [11]. The most difficult step during model checking using FRAIGs is the elimination of existential quantifiers. As in [13], [14], =-=[15]-=- existential quantifiers ∃xf are eliminated by replacing them by f|x=0 +f|x=1. Of course, in the worst case the elimination of one quantifier may double the size of the representation. Although it is ... |

3 |
DAG-aware AIG rewriting
- Mishchenko, Chatterjee, et al.
(Show Context)
Citation Context ..., our prototype implementation will also profit from the integration of a number of interesting ideas recently developed for optimizing AIG representations such as DAG-aware circuit compression [23], =-=[24]-=- and advanced rewriting methods [15], [24]. In the future we will investigate whether methods for structural SAT solving [9] will be useful in our context and we will explore whether it sometimes make... |

2 |
and SAT-Based Model Checking
- “Interpolation
- 2003
(Show Context)
Citation Context ...cceed in limiting the increase in size by several measures including a clever choice of the order of quantifications (‘quantifier scheduling’). Interestingly, in contrast to a widespread belief [16], =-=[17]-=-, [18] our results prove that – for our approach – quantifier elimination by a circuit-based computation of f|x=0 + f|x=1 is not restricted to models with a small number of inputs (which have to be qu... |

1 |
Collection of benchmarks.” [Online]. Available: http://www.informatik.uni-freiburg.de/∼pigorsch/benchmarks.html
- Pigorsch, Scholl
(Show Context)
Citation Context ...he CTL formula φ = AG ( ′′ R2 :=R0⊕R1 ′′ → ( (AX) 2R0+(AX) 2R1 ≡(AX) 3 )) R2 5 The number of registers in the barrelshifter was increased from 4 to 10. 6 The complete set of benchmarks is provided in =-=[22]-=-. 7 The bit width of all operations and registers for palu12,4 is 12, for palu14,4 14 and for palu16,4 16, respectively. (similar to formula (1) from [3]). 8 The benchmarks named ‘decayn’ contain regi... |