IEEE 2007 Custom Intergrated Circuits Conference (CICC) A 1V 10b 30MSPS Switched-RC Pipelined ADC
by
Gil-cho Ahn
,
Min Gyu Kim
,
Pavan Kumar Hanumolu
,
Un-ku Moon
BibTeX
@MISC{Ahn_ieee2007,
author = {Gil-cho Ahn and Min Gyu Kim and Pavan Kumar Hanumolu and Un-ku Moon},
title = {IEEE 2007 Custom Intergrated Circuits Conference (CICC) A 1V 10b 30MSPS Switched-RC Pipelined ADC},
year = {}
}
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Abstract
Abstract — A 10b 30MS/s pipelined ADC using fully-differential switched-RC multiplying digital-to-analog converter (MDAC) is presented. It utilizes a resistive loop to reset the feedback capacitor in the MDAC without using the �oating switch. The measured differential and integral nonlinearities of the prototype IC fabricated in a 0.13µm CMOS process are less than 0.54 LSB and 1.75 LSB respectively. The prototype ADC achieves 51.6dB SNDR and 65.9dB SFDR with 1V supply while consuming 17mW power. I.
Citations
| 37 | A 10-b 20Msample/s analog-to-digital converter - Lewis, Fetterman, et al. - 1992 |
| 14 | Switched opamp: An approach to realize full CMOS SC circuits at very low supply voltages - Crols, Steyaert - 1994 |
| 5 | A 1.4-V 10-bit 25 MSPS pipelined ADC using opamp-reset switching technique - Chang, Moon - 2003 |
| 5 | A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR - Jipeng, Ahn, et al. - 2005 |
| 2 | et al, “A 0.6-V 82-dB Delta-Sigma Audio ADC Using Switched-RC Integrators - Ahn - 2005 |
| 1 | et al., “A 0.9V 92dB double-sampled switched-RC ∆Σ audio ADC - Kim - 2006 |
