## Power Supply Design Parameters for Switching-Noise Control in Deep-Submicron Circuits Design Flows (2001)

Citations: | 1 - 0 self |

### BibTeX

@MISC{Graziano01powersupply,

author = {M. Graziano and M. Delaurenti and G. Masera and G. Piccinini and M. Zamboni},

title = {Power Supply Design Parameters for Switching-Noise Control in Deep-Submicron Circuits Design Flows},

year = {2001}

}

### OpenURL

### Abstract

In the high performance integrated circuits phenomena like crosstalk, IR drops, electromigration and ground bounce are assuming increasing proportions because of the growing complexity in ultra deep submicron designs: their consequences are assuming increasing dimensions compromising circuits functionality and not only their performances. This paper suggests a...

### Citations

465 |
Circuits, Interconnections, and Packaging for VLSI
- Bakoglu
- 1990
(Show Context)
Citation Context ...order of half a clock period the probability of a logic error is highly increased. 2.2. Countermeasures When noise and EMI problems, mainly due to output buffers towards output pads, were first faced =-=[3]-=-, external bypass capacitors were used to supply current to the IC, shortening the current path. This method is no longer satisfactory, basically since, if the amount of current increases and if the d... |

111 | Power Supply Noise Analysis Methodology for Deep-Submicron
- Chen, Ling
- 1997
(Show Context)
Citation Context ...hysic and circuital phenomena and its impact and complexity grow with UDSM integration. Without the purpose of giving an exhaustive exploration of noise in deep-submicron circuits (for which see also =-=[7, 9, 32, 37]-=-), in the following we will consider the relationship among high performance issues and noise effects due to power supply lines [19, 20, 29, 31, 28]. Transistor sizes scaling down implies overall an i... |

77 |
Device electronic for integrated circuits
- Muller, Chan
- 2003
(Show Context)
Citation Context ...resistance and an inductance. This is exactly the condition in which the model reported in the following paragraphs has been developed. Using indeed a substrate doped p-type with NA = 2 · 10 15 cm ��=-=�3 [27], for examp-=-le, its resistivity will be as in equation (4) ρ � (qNAµp) −1 � 6.5 Ω · cm (4) and as a consequence the relaxation frequency computed using the expression in (1) will be as in (5) fr = 1.23... |

72 | Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
- Ismail, Friedman
- 2000
(Show Context)
Citation Context ... Second, high frequency is associated to decreased clock rise times: this relates to higher L dI dt due to on chip and package inductances, having as a result a further worsening of supply references =-=[18]-=-. Besides, technology scaling down involves interconnections too and power supply lines in particular: as line width shrinks, the number of squares increases, causing an increment in the total resista... |

60 | Electromigration – A brief survey and some recent results
- Black
- 1969
(Show Context)
Citation Context ...tivity with two different consequences. First, the higher frequency of current peaks makes life time of metal strips lower due to the increased electromigration risk. Time-to-failure of a metal strip =-=[5]-=-, indeed, depends directly on the average current density; but it is influenced by the temperature as well, that depends on the RMS current: this varies for different frequencies of the peaks [4]. Sec... |

48 | Fast Power Grid Simulation
- Nassif, Kozhaya
- 2000
(Show Context)
Citation Context ...n of noise in deep-submicron circuits (for which see also [7, 9, 32, 37]), in the following we will consider the relationship among high performance issues and noise effects due to power supply lines =-=[19, 20, 29, 31, 28]-=-. Transistor sizes scaling down implies overall an increased number of gates without total chip area changes. Considering a standard cell layout style, this means a greater number of gates on a row; t... |

45 |
Thermal effects in deep sub-micron VLSI interconnects
- Banerjee
- 2000
(Show Context)
Citation Context ...trip [5], indeed, depends directly on the average current density; but it is influenced by the temperature as well, that depends on the RMS current: this varies for different frequencies of the peaks =-=[4]-=-. Second, high frequency is associated to decreased clock rise times: this relates to higher L dI dt due to on chip and package inductances, having as a result a further worsening of supply references... |

36 |
An efficient inductance modeling for on-chip interconnects
- He, Chang, et al.
- 1999
(Show Context)
Citation Context ...f a wire, especially with the growing circuit complexity. Actual inductance evaluation is still an unresolved problem and is one of the more challenging issues discussed both in industry and academia =-=[6, 26]. -=-Although 3D electromagnetic full wave solvers are available, they cannot manage the complexity of today’s integrated circuits. To model the inductive effects of intermediate buses a fast automated i... |

33 | Getting to the Bottom of Deep Submicron II: a global wiring paradigm
- Sylvester, Keutzer
- 1999
(Show Context)
Citation Context ...hysic and circuital phenomena and its impact and complexity grow with UDSM integration. Without the purpose of giving an exhaustive exploration of noise in deep-submicron circuits (for which see also =-=[7, 9, 32, 37]-=-), in the following we will consider the relationship among high performance issues and noise effects due to power supply lines [19, 20, 29, 31, 28]. Transistor sizes scaling down implies overall an i... |

32 |
The future of interconnection technology
- Theis
- 2000
(Show Context)
Citation Context ...htly different times, at least enough to keep the problem within the noise budget [13]. Another efficient measure adopted to decrease wire resistance is to use copper metalization instead of aluminum =-=[37, 38]-=-. Finally electromigration failures can be reduced in several ways. The basic idea in all approaches is to reduce the average current density in a metal segment. These topological and technological so... |

29 |
Analytical modeling and characterization of deep-submicrometer interconnect
- Sylvester, Hu
- 2001
(Show Context)
Citation Context ...y each foundry and on current flowing along the line. Another parameter that influences the global line resistance is skin effect, which increases the effective resistance values if frequency is high =-=[11]-=-. At DC, indeed, the charge carriers have an even distribution throughout the section of the wire. As the frequency increases, a rotational magnetic field around the conductor induces a current in the... |

29 | Analysis of performance impact caused by power supply noise in deep submicron devices
- Jiang, Cheng
- 1999
(Show Context)
Citation Context ...n of noise in deep-submicron circuits (for which see also [7, 9, 32, 37]), in the following we will consider the relationship among high performance issues and noise effects due to power supply lines =-=[19, 20, 29, 31, 28]-=-. Transistor sizes scaling down implies overall an increased number of gates without total chip area changes. Considering a standard cell layout style, this means a greater number of gates on a row; t... |

28 | On-chip inductance Modeling and analysis
- Gala, Zolotov, et al.
(Show Context)
Citation Context ...e is risen. Finding the inductance is not as simple as for the resistance. Indeed, it doesn’t depend only on the technology, but also on the physical layout and on the influence of neighbouring wire=-=s [21]-=-. Inductance effects are due to the generation of a magnetic field for the presence of time-varying currents along a path, and, normally the path considered is a loop: the flux arisen is proportional ... |

28 |
Automatic Synthesis of Low-Power Gated-Clock Finite-State Machines
- Benini, Siegel, et al.
- 1996
(Show Context)
Citation Context ...us to reduce excess performances: adjusting transistor size for minimal cost, or operating the circuits inside a chip at a low voltage, or inactivating part of the circuit by halting the clock signal =-=[22]-=-. Another different attempt is to stagger the gates that are switching together such that they switch at slightly different times, at least enough to keep the problem within the noise budget [13]. Ano... |

27 |
Analysis and Solutions for Switching Noise Coupling in Mixed-Signal ICs
- Aragones, Gonzalez, et al.
- 1999
(Show Context)
Citation Context ...y, in mixed-signal designs analog circuitry suffers from power supply ground bounce injected into the substrate via bulk contacts, reverse biased PN junctions acting as capacitances, and body effects =-=[2]-=-,[39]. To corroborate the importance of power supply noise we realized a set of simulations of a row of cells increasing in number (figure 1). The power busses are modeled with parasitic impedances di... |

22 | Simulation and optimization of the power distribution network in VLSI circuits
- Bai, Bobba, et al.
- 2000
(Show Context)
Citation Context ...valuation in the switching noise (LdI/dt) term. Different works have addressed this point, first for power estimation evaluation, and, recently, for IR drop analysis and for power supply lines design =-=[28, 31, 12]-=-. Considering an exhaustive simulation extremely expensive to be inserted in a cad design algorithm, more approximated different evaluation techniques have been developed. One is the generation of tes... |

22 |
Decoupling capacitor calculations for cmos circuits
- Smith
- 1994
(Show Context)
Citation Context ...n it. Unfortunately, as a drawback the chip footprint increases. To elude this, the capacitors are being formed in unused space, such as under power supply or ground wiring, and filling empty regions =-=[35]-=-. However as the noise problem increases, a larger and larger amount of area should be devoted to capacitors; additionally, perimeter capacitors can decouple the circuit from the package and from the ... |

20 | Multi-pad power/ground network design for uniform distribution of ground bounce
- Oh, Pedram
- 1998
(Show Context)
Citation Context ...n of noise in deep-submicron circuits (for which see also [7, 9, 32, 37]), in the following we will consider the relationship among high performance issues and noise effects due to power supply lines =-=[19, 20, 29, 31, 28]-=-. Transistor sizes scaling down implies overall an increased number of gates without total chip area changes. Considering a standard cell layout style, this means a greater number of gates on a row; t... |

18 |
Simultaneous Switching Noise of CMOS Devices and Systems
- Senthinathan, Prince
- 1994
(Show Context)
Citation Context ...hysic and circuital phenomena and its impact and complexity grow with UDSM integration. Without the purpose of giving an exhaustive exploration of noise in deep-submicron circuits (for which see also =-=[7, 9, 32, 37]-=-), in the following we will consider the relationship among high performance issues and noise effects due to power supply lines [19, 20, 29, 31, 28]. Transistor sizes scaling down implies overall an i... |

13 | Noise considerations in circuit optimization
- Conn, Haring, et al.
- 1998
(Show Context)
Citation Context |

13 | On chip inductance issues in multiconductor systems
- Morton
- 1999
(Show Context)
Citation Context ...f a wire, especially with the growing circuit complexity. Actual inductance evaluation is still an unresolved problem and is one of the more challenging issues discussed both in industry and academia =-=[6, 26]. -=-Although 3D electromagnetic full wave solvers are available, they cannot manage the complexity of today’s integrated circuits. To model the inductive effects of intermediate buses a fast automated i... |

12 |
Measurements and Analyses of Substrate Noise Waveform
- Nagata, Kashima, et al.
- 1999
(Show Context)
Citation Context ...of the flux through the loop of the magnetic field produced by the current to the current itself. Since in general the substrate is not conductive enough (at high frequency it behaves as an insulator =-=[24]-=-) to prevent penetration by the magnetic field, the loop will have a height equal to the substrate thickness (see figure 4). An empirical extremely simple expression for per unit length inductance of ... |

12 |
CMOS digital circuit technology
- Shoji
- 1988
(Show Context)
Citation Context ...ation by the magnetic field, the loop will have a height equal to the substrate thickness (see figure 4). An empirical extremely simple expression for per unit length inductance of a line is found in =-=[34, 40] and rep-=-orted in equation 9: L = µ 2π ln � � 8h w + w 4h where H is the height of the loop. Notice that in general h ≫ w: this means that varying the line width has a small influence on the per unit l... |

7 |
Analysis of interconnection delay on very high-speed LSI/VLSI chips using an MIS microstrip line model
- HASEGAWA, SEKI
(Show Context)
Citation Context ...heavy in terms of computational complexity. For this reason in §3.1 will be overviewed the parasitic parameters relative to a single segment of the power line, without the purpose being complete (see=-= [17]).-=- An accurate model can be inserted in the reasoning reported in the core of this paper without twisting the proposed methodology. The line model used will be considered in §3.2 and in §3.3, while fu... |

6 |
EMI-noise analysis under ASIC design environment
- Hayashi, Yamada
- 2000
(Show Context)
Citation Context ...rmore a global issue connected with supply lines is EMI radiation towards neighbour circuits caused by high-frequency current. Basically it is possible to distinguish three different mechanisms [41], =-=[33]-=-. One is the direct radiation from the chip surface: high frequency current flows through metal wires inside a chip and acts as antennae. The second effect is conducting noise from the signal ports of... |

5 | Noise-constrained performance optimization by simultaneous gate and wire sizing based on lagrangian relaxation
- Jiang, Jou, et al.
- 1999
(Show Context)
Citation Context |

4 |
Low delta-I noise CMOS circuits based on differential logic and current limiters
- Gonzalez, Rubio
- 1999
(Show Context)
Citation Context ...gnal [22]. Another different attempt is to stagger the gates that are switching together such that they switch at slightly different times, at least enough to keep the problem within the noise budget =-=[13]-=-. Another efficient measure adopted to decrease wire resistance is to use copper metalization instead of aluminum [37, 38]. Finally electromigration failures can be reduced in several ways. The basic ... |

2 | Substrate modeling and lumped substrate resistance extraction for cmos esd/latchup circuit simulation
- Li, Rosenbaum, et al.
- 1999
(Show Context)
Citation Context ...n mixed-signal designs analog circuitry suffers from power supply ground bounce injected into the substrate via bulk contacts, reverse biased PN junctions acting as capacitances, and body effects [2],=-=[39]-=-. To corroborate the importance of power supply noise we realized a set of simulations of a row of cells increasing in number (figure 1). The power busses are modeled with parasitic impedances distrib... |

2 | Electromagnetic modeling and signal integrity simulation of power/ground networks in high speed digital packages and printed circuit boards
- Yuan
- 1998
(Show Context)
Citation Context ...Furthermore a global issue connected with supply lines is EMI radiation towards neighbour circuits caused by high-frequency current. Basically it is possible to distinguish three different mechanisms =-=[41]-=-, [33]. One is the direct radiation from the chip surface: high frequency current flows through metal wires inside a chip and acts as antennae. The second effect is conducting noise from the signal po... |

1 |
Design and optimization techniques for high speed VLSI circuits. Ph.d. thesis dissertation, Politecnico di
- Delaurenti
- 1999
(Show Context)
Citation Context ...row) for the capacitor presence. We realized a tool for transistor sizes optimization, designed at first to achieve optimal results, during the creation of a cell library, in terms of speed and power =-=[10]-=-. Being one of its quality the possibility to optimism multiobjective functions, we easily added a noise issue to be analyzed during the optimization phase, without neglecting the original high perfor... |

1 |
Cmos dynamic logic for high speed applications. Master’s project, Politecnico di Torino, Electronic Departement
- Graziano
- 1997
(Show Context)
Citation Context ...ise in the IR drop on voltage reference, if parasitics resistance is considered on a metal line. The spurious GND or VDD signals can affect the functionality of the gate due to three different causes =-=[14]-=-. First, the non-ideality of the references can delay the transistor switching and then can worse the total delay of the gate. Second, spikes on power supply can, by capacitive coupling, change or des... |

1 |
Analysis and optimization of CMOS circuits for high speed and low noise. Ph.d. thesis dissertation, Politecnico di
- Graziano
- 1999
(Show Context)
Citation Context ...ility to the prediction of design parameters; the purpose is its integration in a noise safety design tool that is not explained here because this is not the aim of the paper. Details can be found in =-=[15]-=-. 2.1. The phenomenon 2. Power Supply noise Power supply noise is multi faced, for it involves both physic and circuital phenomena and its impact and complexity grow with UDSM integration. Without the... |

1 |
Noise safety design methodologies
- Graziano, Delaurenti, et al.
- 2000
(Show Context)
Citation Context ...ise behaviour, given technological and circuit parameters. Furthermore it has been studied to be easily inserted in an automated tool having as a purpose noise reductions in high performance circuits =-=[16]-=-. 3. A model for design parameters determination The purpose of the paper is the explanation of an analytical method for generating power supply noise evaluation and design parameters. The final aim, ... |

1 |
On-chip inductance modeling of vlsi inteconnects
- Li, Kleveland, et al.
(Show Context)
Citation Context ...d inductance extraction and verification tool will be necessary. Accurate measurements and modeling show that the inductive effects are more prominent for lines of intermediate lengths (mm-scale): in =-=[23]-=- a coplanar waveguide case, where a signal wire is sandwiched between two ground wires, is considered to evaluate the inductance behaviour. Results show that inductance increases monotonically with th... |

1 |
Parasitic effects due to interconnections in microelectronic design. Ph.d. thesis dissertation, Universitat Politecnica de Catalunya
- Moll
- 1995
(Show Context)
Citation Context ...described by means of its capacitance and conductance: in the following some considerations will be made to further simplify the model. Three modes of operation for the substrate can be distinguished =-=[25]. The dielectri-=-c mode is the operation at high frequencies: in this case we may assume GS = 1/RS = 0 and consider just the substrate as 7 alog.tex; 29/01/2001; 15:08; p.7s8 metal lines¡ ¡ ¡ ¡ ¡s¢¡¢¡¢¡... |

1 |
On-chip decoupling capacitor optimization usign architectural level current signature prediction
- Pant, Pant, et al.
- 2000
(Show Context)
Citation Context ...on the trend is the insertion of distributed capacitors as near as possible to the gates forming circuit blocks critical from the point of 5 alog.tex; 29/01/2001; 15:08; p.5s6 view of switching noise =-=[30]-=-. The authors give in this paper some design parameters for the optimized insertion of distributed capacitors. The parallel approach has been thus to reduce excess performances: adjusting transistor s... |

1 |
Current signature compression for ir-drop analysis
- Chaundhry, Panda, et al.
- 2000
(Show Context)
Citation Context |

1 |
distribution system design methodology and capacitor selection for modern cmos technology
- Power
- 1999
(Show Context)
Citation Context ...hould be devoted to capacitors; additionally, perimeter capacitors can decouple the circuit from the package and from the external circuitry but are not able to avoid IR drop inside the circuit block =-=[36]-=-. For this reason the trend is the insertion of distributed capacitors as near as possible to the gates forming circuit blocks critical from the point of 5 alog.tex; 29/01/2001; 15:08; p.5s6 view of s... |