Abstract

This paper focuses on testing sequential circuits using a simple form of signature analysis as a compaction technique. More specifically, the paper describes a systematic methodology for calculating the probability of aliasing when a randomly generated test input vector sequence is applied to a given finite state machine (FSM) and the final FSM output is used to verify the functionality of the FSM. We also explore how the aliasing probability is affected when the output mapping (from the set of states to the set of outputs) of the FSM under test changes.

Citations