Fast Instruction Cache Simulation Strategies in a Hardware/Software Co-Design Environment (1999)
| Venue: | Proc. Asia South Pacific Design Automation Conference |
| Citations: | 5 - 4 self |
BibTeX
@INPROCEEDINGS{Lajolo99fastinstruction,
author = {Marcello Lajolo and Luciano Lavagno and Alberto Sangiovanni-Vincentelli},
title = {Fast Instruction Cache Simulation Strategies in a Hardware/Software Co-Design Environment},
booktitle = {Proc. Asia South Pacific Design Automation Conference},
year = {1999},
pages = {347--350}
}
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Abstract
Cache memories are one of the main factors that aect software performance, and their use is becoming increasingly common even in embedded systems. Ecient analysis of the eects of parameter variations (cache dimensions, degree of associativity, replacement policy, line size, . . . ) is at the same time an essential and very time-consuming aspect of embedded system design, whose complexity increases when multi-tasking and real-time aspects must be considered.
Citations
| 152 | HardwareSoftware Co-Design of Embedded Systems: The Polis Approach - Balarin, Chiodo, et al. - 1997 |
| 78 | Generation and analysis of very long address traces - Borg, Wall - 1990 |
| 37 | Efficient software performance estimation methods for hardware/software codesign - Suzuki, Sangiovanni-Vincentelli - 1996 |
| 30 | Cache Evaluation and the Impact of Workload Choice - Smith - 1985 |
| 4 | Cache Sampling by Sets - Lui, Peir - 1993 |
