AN EXPLORATION METHODOLOGY FOR VLIW ARCHITECTURE TARGETING MULTIMODE WIRELESS BASEBAND PROCESSING

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AN EXPLORATION METHODOLOGY FOR VLIW ARCHITECTURE TARGETING MULTIMODE WIRELESS BASEBAND PROCESSING

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by Thomas Schuster , Bruno Bougard , David Novo Bruna , Emil Matus , Liesbet Van Der Perre , Gerhard Fettweis

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BibTeX

@MISC{Schuster_anexploration,
    author = {Thomas Schuster and Bruno Bougard and David Novo Bruna and Emil Matus and Liesbet Van Der Perre and Gerhard Fettweis},
    title = {AN EXPLORATION METHODOLOGY FOR VLIW ARCHITECTURE TARGETING MULTIMODE WIRELESS BASEBAND PROCESSING},
    year = {}
}

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Abstract

The wide range of future and existing standards in wireless communications calls for flexible solutions. A way to introduce flexibility to digital radio systems is to replace hardwired components by programmable devices. This paper describes the exploration of a VLIW architecture targeting the domain of multimode wireless baseband processing. Target is to explore the tradeoff between flexibility, performance and power consumption. The Coware ® LISATek ™ tool suite for automated embedded processor design has been used to create a processor model with scalable number of functional units and RTL generation capability. Furthermore, a C-compilation framework based on IMPACT was adapted to enable the mapping of a Fast Fourier Transformation and parts of a SDM-OFDM receiver. The code was optimized with special instruction supported in C by intrinsic functions. To estimate the costs of the implemented optimization, the generated RTL has been synthesized in 90nm technology. It is shown that a wide energy-performance tradeoff can be ranged by varying the processor configurations. Moreover, by using special instructions for complex arithmetic, power consumption and execution time of the benchmarked kernels can be reduced by factor two. 1.

Keyphrases

power consumption special instruction hardwired component rtl generation capability sdm-ofdm receiver wireless communication multimode wireless baseband processing processor configuration benchmarked kernel wide range coware lisatek tool suite implemented optimization c-compilation framework flexible solution programmable device scalable number fast fourier transformation wide energy-performance tradeoff intrinsic function vliw architecture complex arithmetic execution time digital radio system functional unit processor model processor design

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