## Contents

### Abstract

(Date)

### Citations

165 |
TILOS: A posynomial programming approach to transistor sizing
- Fishburn, Dunlop
- 1985
(Show Context)
Citation Context ...e optimization of digital integrated circuits has been used for quite some time [Ruehli77] and has developed into three major forms: heuristic, analytical, and hybrid. Heuristic methods such as TILOS =-=[Fishburn85]-=- and [Lin90] generally perform this optimization by iteratively optimizing the critical path while employing a heuristic to resize gates along the path, terminating when there are no more candidates. ... |

94 |
Standard for binary floating-point arithmetic
- IEEE
- 1985
(Show Context)
Citation Context ...from the optimizer will be left as continuous sizes. 6.1 Double‐Precision Floating Point Unit The FPU that will be the subject of our study takes in three IEEE double-precision floating point numbers =-=[IEEE85]-=-, A, B, and C, and outputs (A x B) + C in normalized double-precision format. This architecture is very similar to the FPU implemented in IBM’s Power6 microprocessor [Curran06]. Figure 6-1 illustrates... |

81 |
Power consumption estimation in CMOS VLSI chips
- Liu, Svensson
- 1994
(Show Context)
Citation Context ...ibution is not included in our analysis but could be potentially modeled as a posynomial that is dependent on total area of the circuit, H-tree partitioning, and a clock driver ratio, such as done by =-=[Liu94]-=-. Such information should be available to the optimizer since the optimizer is executed post-synthesis. Finally, only a single variety of flip-flop with three drive strengths is considered in our mode... |

38 | An efficient algorithm for statistical minimization of total power under timing yield constraints
- Mani, Devgan, et al.
- 2005
(Show Context)
Citation Context ...ch specifies the affinity of the gate choice between the current gate size and the next best gate size. The LP is then solved and the next best gate is used if γv is greater than 0.99. [Nguyen03] and =-=[Orshansky05]-=- perform energy minimization by jointly assigning threshold voltages and gate sizes in an iterative approach that optimizes slack distribution among the gates followed by exhaustive local search for i... |

31 | Methods for true energy-performance optimization
- Marković, Stojanović, et al.
- 2004
(Show Context)
Citation Context ...ements. Based on analysis of these two plots, it can be concluded that energy-performance optimization of multiple blocks connected together involves a balance of energy and delay between the blocks. =-=[Markovic04]-=- uses the notion of hardware sensitivity to formalize the tradeoff between these blocks. Hardware sensitivity is defined as the absolute gradient of energy to delay. At an optimal design-point, the ha... |

25 |
Community Effort
- Butler, Sproull, et al.
- 2002
(Show Context)
Citation Context ...zes are not fixed, the delay and energy of the circuit is still relatively stable. This indicates that the optima for minimum delay gate sizing is wide and is in agreement with theoretical results in =-=[Sutherland99]-=-. The unconstrained delay minimization using local fit parameters is able to arrive at a design point that is much better than the global optimum point obtained using global fit parameters. This motiv... |

16 | Timing and area optimization for standard-cell VLSI circuit design
- Chuang, Sapatnekar, et al.
- 1995
(Show Context)
Citation Context ... available from the standard cell library. Hybrid methods try to recover the loss in optimality from the rounding process by applying non-linear optimization or heuristics on the analytical solution. =-=[Chuang95]-=- solves the analytical optimization problem as a linear program and uses a branch-andbound algorithm to move from the continuous solution to a discrete solution. Recently [Hu07] demonstrated a hybrid ... |

16 | Gate sizing: a general purpose optimization approach
- Coudert
- 1996
(Show Context)
Citation Context ..., near-critical paths do affect the timing of the critical path if they are in the fanout of that path. The omission of these paths in the greedy gate sizing selection results in sub-optimal results. =-=[Coudert96]-=- considers all paths in the 1soptimization by performing a multi-dimension descent-based optimization employing a heuristic to limit the computational complexity of gradient recomputation. [Chinnery05... |

13 |
Algorithms for library-specific sizing of combinational logic
- Chan
- 1990
(Show Context)
Citation Context ...ese algorithms are susceptible to being trapped in local minima and are unable to guarantee global optimality. Realizing that the energy-performance optimization of discrete-sized gates is NPcomplete =-=[Chan90]-=-, researchers set out to produce better analytical solutions by relaxing the constraint of discrete sizes. This relaxation allows the formulation of the optimization in a form that can be solved effic... |

10 |
A tutorial on geometric programming,” Optimization and Engineering
- Boyd, Kim, et al.
- 2007
(Show Context)
Citation Context ...ving the problem of going from a continuous solution to a discrete solution mainly due to the fact that standard cell libraries only offer sparse choices of gate sizes. 4.2 Round and Resize Algorithm =-=[Boyd07]-=- proposes a more sophisticated rounding algorithm which solves the geometric program multiple times but rounds and fixes parameters to discrete sizes if they are within 10% of the closest discrete gat... |

9 |
Delay and Area Optimization in Standard-Cell Design
- Lin, Marek-Sadowska, et al.
- 1990
(Show Context)
Citation Context ... digital integrated circuits has been used for quite some time [Ruehli77] and has developed into three major forms: heuristic, analytical, and hybrid. Heuristic methods such as TILOS [Fishburn85] and =-=[Lin90]-=- generally perform this optimization by iteratively optimizing the critical path while employing a heuristic to resize gates along the path, terminating when there are no more candidates. Unfortunatel... |

8 | Linear Programming for Sizing, Vth and Vdd Assignment
- Chinnery, Keutzer
(Show Context)
Citation Context ...[Coudert96] considers all paths in the 1soptimization by performing a multi-dimension descent-based optimization employing a heuristic to limit the computational complexity of gradient recomputation. =-=[Chinnery05]-=- formulates the gate sizing problem as a linear program (LP) with cell-choice variables γv � [0,1], for each gate v, which specifies the affinity of the gate choice between the current gate size and t... |

6 |
A 250ps 64-bit carry-lookahead adder
- Kao, Zlatanovici, et al.
- 2006
(Show Context)
Citation Context ...problem as a geometric program, guarantees global optimality of the result and has been used to design high performance circuits such as a 250ps 64-bit Carry-Lookahead adder in a 90nm CMOS technology =-=[Kao06]-=-. The existing delay models that are employed in [Zlatanovici06] are accurate to a few picoseconds from tabulated values which make it useful for designing full-custom integrated circuits where the si... |

6 |
Analytical power/timing optimization technique for digital system
- Ruehli, Wol
- 1977
(Show Context)
Citation Context ...lier and a pipelined double-precision floating point unit. 1.1 Background and current state of the art Energy-performance optimization of digital integrated circuits has been used for quite some time =-=[Ruehli77]-=- and has developed into three major forms: heuristic, analytical, and hybrid. Heuristic methods such as TILOS [Fishburn85] and [Lin90] generally perform this optimization by iteratively optimizing the... |

5 | Gate Sizing For Cell Library-Based Designs
- Hu, Ketkar, et al.
- 2009
(Show Context)
Citation Context ...alytical solution. [Chuang95] solves the analytical optimization problem as a linear program and uses a branch-andbound algorithm to move from the continuous solution to a discrete solution. Recently =-=[Hu07]-=- demonstrated a hybrid method which first solves a geometric program of the relaxed optimization problem and performs dynamic programming to arrive at a discrete solution using the analytical solution... |

5 |
Impact of Layout on
- Pang, Nikolic
(Show Context)
Citation Context ...pically much greater than junction leakage [Keshavarzi00]. However, this assumption might not hold true for future scaled technologies which exhibit increased layout-induced variations as measured by =-=[Pang06]-=-. 17s� ������ � ∑ � ����,�� �� ��� ����� Equation (3-4) provides the energy model for static energy of the circuit. Pleak,i corresponds to the leakage power of a unit-sized version of the correspondin... |

4 |
Intrinsic Leakage in Deep Submicron CMOS IC-measurement-based Test Solutions
- Keshavarzi, Roy, et al.
- 2000
(Show Context)
Citation Context ... drive strengths. We can therefore assume a linear dependence between leakage energy and gate sizing because sub-threshold conduction and gate leakage are typically much greater than junction leakage =-=[Keshavarzi00]-=-. However, this assumption might not hold true for future scaled technologies which exhibit increased layout-induced variations as measured by [Pang06]. 17s� ������ � ∑ � ����,�� �� ��� ����� Equation... |

4 |
et al., “Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization
- Nguyen
- 2003
(Show Context)
Citation Context ...ach gate v, which specifies the affinity of the gate choice between the current gate size and the next best gate size. The LP is then solved and the next best gate is used if γv is greater than 0.99. =-=[Nguyen03]-=- and [Orshansky05] perform energy minimization by jointly assigning threshold voltages and gate sizes in an iterative approach that optimizes slack distribution among the gates followed by exhaustive ... |

3 |
et al, “4GHz+ Low-Latency Fixed-Point and Binary Floating-Point Execution Units for the POWER6
- Curran
- 2006
(Show Context)
Citation Context ...on floating point numbers [IEEE85], A, B, and C, and outputs (A x B) + C in normalized double-precision format. This architecture is very similar to the FPU implemented in IBM’s Power6 microprocessor =-=[Curran06]-=-. Figure 6-1 illustrates the block-level diagram of the FPU datapath. Only the logic blocks involved in processing the mantissa are included in this diagram. There is an exponent datapath (not illustr... |

2 |
Whan: “Gradient - based optimization of custom circuits using a static timing formulation
- Conn, Elfadel, et al.
- 1999
(Show Context)
Citation Context ...f discrete sizes. This relaxation allows the formulation of the optimization in a form that can be solved efficiently, producing a result that is as accurate as the analytical models used, such as in =-=[Conn99]-=-. Furthermore, recognizing that convex models such as the Elmore delay model used in TILOS can be solved exactly using convex optimization; there has been renewed interest in modeling this optimizatio... |

2 |
Retiming synchronous circuitry. Algoritmica 6
- Leiserson, Saxe
- 1991
(Show Context)
Citation Context ...y replacing the “delay” of the combinational circuit with the “cycle time” of the sequential circuit. A sequential circuit can be represented as a directed acyclic graph (DAG) G(V,E) as introduced by =-=[Leiserson91]-=-. Each element vi in V corresponds to a combinational logic gate in the sequential circuit with two special source and sink nodes representing inputs and outputs of the circuit respectively. Each edge... |

2 | Power-performance optimization for digital circuits
- Zlatanovici
- 2006
(Show Context)
Citation Context ...ved exactly using convex optimization; there has been renewed interest in modeling this optimization problem as a geometric program (GP) which can be solved for global optimum such as in [Boyd05] and =-=[Zlatanovici06]-=-. This interest is fueled by the recent availability of fast 2sinterior-point method based optimizers such as [Mosek07] which provide the user with flexibility in formulating the digital circuit optim... |

1 |
Automatic Generation of Standard Cell
- Hashimoto, Fujimori, et al.
- 2004
(Show Context)
Citation Context ...ries. There are also standard cell libraries that automatically generate cells based on required drive strengths, which effectively provides a standard cell library with continuous gate sizes such as =-=[Hashimoto04]-=-. 6s2.1 Synopsys Non‐linear Delay Model (NLDM) The commonly used commercial gate delay model is Synopsys Non-linear Delay Model (NLDM), which is a two-dimensional lookup table for gate delay and outpu... |

1 |
et al, “65nm LP/GP mix low cost platform for multi-media wireless and consumer applications
- Tavel
- 2005
(Show Context)
Citation Context ...n CMOS processes typically provide the circuit designer with a variety of options such as low power (LP) and general purpose (G) transistors which are optimized for different performance requirements =-=[Tavel06]-=-. Circuit designers also have the option of choosing from a variety of threshold voltages. An LP transistor is ideal for low performance circuits because leakage currents of these transistors are much... |