## Interconnect Layout Optimization under Higher-Order RLC Model for MCM Designs (1997)

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Venue: | IN PROC. INT. CONF. ON COMPUTER AIDED DESIGN |

Citations: | 26 - 4 self |

### BibTeX

@INPROCEEDINGS{Cong97interconnectlayout,

author = {Jason Cong and Cheng-Kok Koh and Patrick H. Madden},

title = {Interconnect Layout Optimization under Higher-Order RLC Model for MCM Designs},

booktitle = {IN PROC. INT. CONF. ON COMPUTER AIDED DESIGN},

year = {1997},

pages = {713--720},

publisher = {}

}

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### Abstract

### Citations

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Citation Context ...ntation, we introduce the notion of a reduced tree representation to allow topologies to share common subtopologies. This is analogous to the concept of reduced orderedbinary decision diagram (ROBDD) =-=[28]-=- that is commonly used in logic synthesis. We illustrate the idea of a reduced tree representation in Figure 2. Consider two topologies T1 and T 42 that correspond to the same interconnect structure w... |

459 |
Asymptotic Waveform Evaluation for Timing Analysis
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Citation Context ... are poles and k j’s are residues, all of which can be determined uniquely by matching the initial boundary conditions, denoted m 1 i , and the first 2q ff 1 moments m j i of Hisssto those of ˆHisss=-=[22]-=-. The choice of order q depends on the accuracy required but is always much less than the order of the circuit. In practice, q ffi 5 is commonly used. When q is chosen to be two, it is known as the tw... |

411 |
The Transient Response of Damped Linear Networks with Particular Regard to Wide Band Amplifiers
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Citation Context ...ing [18], [28], [29], [34] assumed RC models for the interconnects. With the exceptions of [12], [18], and [29], which considered higher order RC models, all other studies used the Elmore delay model =-=[10]-=-, which accounted for the first order RC effect only. These studies did not consider the inductance effect, a dominant factor in high-speed MCM designs. Our proposed paper overcomes these shortcomings... |

145 |
On Steiner’s Problem with Rectilinear Distance
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- 1966
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Citation Context ...(i.e., i’s are as close to zero as possible) and the total wire-length or wiring area is minimized. III. RATS-TREE ALGORITHM Given a set of terminals, the RATS-tree algorithm operates on a Hanan grid =-=[15]-=- induced by the terminals. Let (xm;ym) denote the coordinates of grid point m and jmj = d(s0;m) denote the Manhattan distance between s0 and m. All Hanan grid points are ordered according to their Man... |

119 | Optimal wire sizing and buffer insertion for low power and a generalized delay model
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- 1996
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Citation Context ...tion such as A trees [7], low-delay trees [1], iterative Dreyfus–Wagner and constructive force-directed Steiner trees [16], non-Hanan routing [17], wire-sizing optimization [3], [6], [7], [11], [12], =-=[27]-=-, [31], as well as the more recent studies that combined topology construction with repeater insertion and/or wire sizing [18], [28], [29], [34] assumed RC models for the interconnects. With the excep... |

111 | Performance optimization of VLSI interconnect layout
- Cong, He, et al.
- 1996
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Citation Context ...formance. Recent studies showed that interconnect performance could be optimized with several techniques, which included topology optimization, wire-sizing optimization, and/or repeater optimization; =-=[9]-=- gave a comprehensive survey of these techniques. However, most of these techniques were applied independently and were based on resistance–capacitance (RC) models that might not be appropriate for mu... |

98 | A New Class of Iterative Steiner Tree Heuristics with Good Performance
- Kahng, Robins
- 1992
(Show Context)
Citation Context ...hat all sinks have the same required arrival time, then an optimal RATS tree is an optimal bounded-radius Steiner tree [4]. Lastly, an optimal RATS tree with unbounded qi’s is an optimal Steiner tree =-=[22]-=-. The path-length formulation captures the delay for unloaded lossless transmission lines in MCM printed circuit board designs perfectly. In this formulation, the output response at the end of an inte... |

78 | Provably good performance-driven global routing
- Cong, Kahng, et al.
- 1992
(Show Context)
Citation Context ... tree is an optimal Steiner arborescence [26]. If we relax the requirement such that all sinks have the same required arrival time, then an optimal RATS tree is an optimal bounded-radius Steiner tree =-=[4]-=-. Lastly, an optimal RATS tree with unbounded qi’s is an optimal Steiner tree [22]. The path-length formulation captures the delay for unloaded lossless transmission lines in MCM printed circuit board... |

70 | Performance-driven interconnect design based on distributedRC
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- 1993
(Show Context)
Citation Context ...MCM designs. Most of the previous results on interconnect optimization were achieved under RC interconnect models for integrated circuit designs only. Studies on topology optimization such as A trees =-=[7]-=-, low-delay trees [1], iterative Dreyfus–Wagner and constructive force-directed Steiner trees [16], non-Hanan routing [17], wire-sizing optimization [3], [6], [7], [11], [12], [27], [31], as well as t... |

65 | Buffered Steiner tree construction with wire sizing for interconnect layout optimization
- Okamoto, Cong
- 1996
(Show Context)
Citation Context ...ding recent studies on topology optimization [2, 3], wiresizing optimization [4, 5, 6, 7], as well as the most recent works that combined topology construction with buffer insertion and/or wiresizing =-=[8, 9, 10]-=-. They did not consider the inductance effect, which may be an important factor in high-speed MCM/PCB designs and high frequency deep sub-micron designs. In this study, we overcome this shortcoming by... |

56 | Optimal wiresizing under the distributed Elmore delay model
- Cong, Leung
- 1995
(Show Context)
Citation Context ...s on topology optimization such as A trees [7], low-delay trees [1], iterative Dreyfus–Wagner and constructive force-directed Steiner trees [16], non-Hanan routing [17], wire-sizing optimization [3], =-=[6]-=-, [7], [11], [12], [27], [31], as well as the more recent studies that combined topology construction with repeater insertion and/or wire sizing [18], [28], [29], [34] assumed RC models for the interc... |

55 | Near-optimal critical sink routing tree constructions
- Boese, Kahng, et al.
- 1995
(Show Context)
Citation Context ...the previous results on interconnect optimization were achieved under RC interconnect models for integrated circuit designs only. Studies on topology optimization such as A trees [7], low-delay trees =-=[1]-=-, iterative Dreyfus–Wagner and constructive force-directed Steiner trees [16], non-Hanan routing [17], wire-sizing optimization [3], [6], [7], [11], [12], [27], [31], as well as the more recent studie... |

55 |
Timing Models for MOS Circuits
- Horowitz
- 1984
(Show Context)
Citation Context ...of order q depends on the accuracy required but is always much less than the order of the circuit. In practice, q ffi 5 is commonly used. When q is chosen to be two, it is known as the two-pole model =-=[23, 11, 24]-=-. From ˆHisss, one can derive the approximated output voltage v̂istsand solve for the transition delay txsisof the output signal at si to reach x% of VDD (assuming a rising output) for the first time.... |

50 | New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing
- Lillis, Cheng, et al.
- 1996
(Show Context)
Citation Context ...n routing [17], wire-sizing optimization [3], [6], [7], [11], [12], [27], [31], as well as the more recent studies that combined topology construction with repeater insertion and/or wire sizing [18], =-=[28]-=-, [29], [34] assumed RC models for the interconnects. With the exceptions of [12], [18], and [29], which considered higher order RC models, all other studies used the Elmore delay model [10], which ac... |

49 |
An edge-based heuristic for Steiner routing
- Borah, Owens, et al.
- 1994
(Show Context)
Citation Context ...erated by our RATS-tree algorithm for one of the randomly generated 9-pin nets for k = 2; 3, and 6. We also include the topology generated by the Borah–Owens–Irwin (BOI) Steiner algorithm proposed by =-=[2]-=-. Both the delay and settling time of each topology are in nanoseconds and TABLE I TRADEOFF AMONG MAXIMUM SINK DELAY, SIGNAL SETTLING TIME, VOLTAGE OVERSHOOT, AND ROUTING COST FOR RATS TREES GENERATED... |

46 | Optimal wire-sizing formula under the Elmore delay model
- Chen, Chen, et al.
- 1996
(Show Context)
Citation Context ...antages: (1) Most of the previous works on interconnect optimization were achieved under RC interconnect models only, including recent studies on topology optimization [2, 3], wiresizing optimization =-=[4, 5, 6, 7]-=-, as well as the most recent works that combined topology construction with buffer insertion and/or wiresizing [8, 9, 10]. They did not consider the inductance effect, which may be an important factor... |

46 | An analytical delay model for RLC interconnects
- Kahng, Muddu
- 1997
(Show Context)
Citation Context ...of order q depends on the accuracy required but is always much less than the order of the circuit. In practice, q ffi 5 is commonly used. When q is chosen to be two, it is known as the two-pole model =-=[23, 11, 24]-=-. From ˆHisss, one can derive the approximated output voltage v̂istsand solve for the transition delay txsisof the output signal at si to reach x% of VDD (assuming a rising output) for the first time.... |

39 | Simultaneous routing and buffer insertion with restrictions on buffer locations - Zhou, Wong, et al. |

30 | Performance driven multi-layer general area routing for PCB/MCM designs
- Cong, Madden
- 1998
(Show Context)
Citation Context ...With MINOTAUR Global Router The ability of the RATS-tree algorithm to generate a set of routing topologies for a timing-critical net complements a performance-driven MCM global router called MINOTAUR =-=[8]-=-, [30]. Presented with a set of candidate routing topologies for each timing-critical net, the MINOTAUR global router has the flexibility to choose a topology from the set of candidate topologies of e... |

27 |
A Performance-Driven Steiner Tree Algorithm Us lobal Ro 6(3
- Hong
(Show Context)
Citation Context ...erconnect models for integrated circuit designs only. Studies on topology optimization such as A trees [7], low-delay trees [1], iterative Dreyfus–Wagner and constructive force-directed Steiner trees =-=[16]-=-, non-Hanan routing [17], wire-sizing optimization [3], [6], [7], [11], [12], [27], [31], as well as the more recent studies that combined topology construction with repeater insertion and/or wire siz... |

27 | Manhattan or Non-Manhattan? A study of alternative VLSI routing architectures - Koh, Madden |

22 | efficient multilayer MCM router based on four-via routing
- Khoo, Cong“An
- 1995
(Show Context)
Citation Context ...atible topologies for different nets, we perform experiments on two Microelectronics and Computer Technology Corporation (MCC) multichip module benchmark circuits mcc1 and mcc2 that have been used in =-=[23]-=-. The distributions of net sizes in mcc1 and mcc2 are shown in Table II [30]. We first construct approximate minimum Steiner tree topologies [2] for nets in mcc1 and mcc2. We sort the pins from these ... |

19 |
A sensitivity-based wiresizing approach to interconnect optimization of lossy transmission line topologies
- Xue, Kuh, et al.
- 1996
(Show Context)
Citation Context ...tures as lossy transmission lines. Under this formulation, the delay at each sink is the sum of the propagation delay tf and the rising/falling (or transition) delay t of the signal response waveform =-=[32]-=- tT(s0;si) =tf (s0;si) + t(s0;si): (1) In this paper, we model the transition delay with a higher order moment-based delay model. More specifically, we use the two-pole-based analytical delay model pr... |

19 | Shaping a VLSI wire to minimize Elmore delay
- Fishburn
- 1997
(Show Context)
Citation Context ...ogy optimization such as A trees [7], low-delay trees [1], iterative Dreyfus–Wagner and constructive force-directed Steiner trees [16], non-Hanan routing [17], wire-sizing optimization [3], [6], [7], =-=[11]-=-, [12], [27], [31], as well as the more recent studies that combined topology construction with repeater insertion and/or wire sizing [18], [28], [29], [34] assumed RC models for the interconnects. Wi... |

15 |
Exact moment matching model of transmission lines and application to interconnect delay estimation
- Yu, Kuh
- 1995
(Show Context)
Citation Context ... 1 m 2 ; if 4m2 i 0 3 m 1 i 2 > 0 2 < 0 2 =0 (2) is the jth order moment of the voltage transfer function of node i. Moments of an RLC interconnect can be computed by the methods proposed in [20] and =-=[33]-=-. In this paper, we present a new approach to moment computation in Section IV. Signal response waveform is another important factor in interconnect design. Under ideal situations, one would prefer th... |

13 |
Performance driven MCM routing using a second order RLC tree delay model
- Sriram, Kang
- 1993
(Show Context)
Citation Context ...lso present a new algorithm to incrementally compute moments of sinks in an RLC tree in a bottom-up manner. (2) A few approaches have proposed to use higher-order RLC models for topology optimization =-=[11, 12]-=-, wiresizing optimization [13], and termination optimization [14, 15, 16]. But none of them can consider all three optimization simultaneously for both delay and signal integrity optimization. Our opt... |

11 |
Two-pole analysis of interconnection trees
- Khang, Muddu
- 1995
(Show Context)
Citation Context ... 1 i 3:90 1 m 2 ; if 4m2 i 0 3 m 1 i 2 > 0 2 < 0 2 =0 (2) is the jth order moment of the voltage transfer function of node i. Moments of an RLC interconnect can be computed by the methods proposed in =-=[20]-=- and [33]. In this paper, we present a new approach to moment computation in Section IV. Signal response waveform is another important factor in interconnect design. Under ideal situations, one would ... |

10 |
High performance multichip interconnection design
- Zhou, Tsui, et al.
- 1993
(Show Context)
Citation Context ...lso present a new algorithm to incrementally compute moments of sinks in an RLC tree in a bottom-up manner. (2) A few approaches have proposed to use higher-order RLC models for topology optimization =-=[11, 12]-=-, wiresizing optimization [13], and termination optimization [14, 15, 16]. But none of them can consider all three optimization simultaneously for both delay and signal integrity optimization. Our opt... |

10 |
Shaping a VLSI wire to minimize delay using transmission line model
- Gao, Wong
- 1998
(Show Context)
Citation Context ...timization such as A trees [7], low-delay trees [1], iterative Dreyfus–Wagner and constructive force-directed Steiner trees [16], non-Hanan routing [17], wire-sizing optimization [3], [6], [7], [11], =-=[12]-=-, [27], [31], as well as the more recent studies that combined topology construction with repeater insertion and/or wire sizing [18], [28], [29], [34] assumed RC models for the interconnects. With the... |

10 | Non-Hanan routing
- Hou, Hu, et al.
- 1999
(Show Context)
Citation Context ...egrated circuit designs only. Studies on topology optimization such as A trees [7], low-delay trees [1], iterative Dreyfus–Wagner and constructive force-directed Steiner trees [16], non-Hanan routing =-=[17]-=-, wire-sizing optimization [3], [6], [7], [11], [12], [27], [31], as well as the more recent studies that combined topology construction with repeater insertion and/or wire sizing [18], [28], [29], [3... |

9 |
Pillage, “RC interconnect synthesis —- a moment fitting appraoch
- Menezes, Pullela, et al.
- 1994
(Show Context)
Citation Context ...antages: (1) Most of the previous works on interconnect optimization were achieved under RC interconnect models only, including recent studies on topology optimization [2, 3], wiresizing optimization =-=[4, 5, 6, 7]-=-, as well as the most recent works that combined topology construction with buffer insertion and/or wiresizing [8, 9, 10]. They did not consider the inductance effect, which may be an important factor... |

8 | Pillage, “RC interconnect synthesis–a moment fitting approach
- Menezes, Pullela, et al.
- 1994
(Show Context)
Citation Context ...uch as A trees [7], low-delay trees [1], iterative Dreyfus–Wagner and constructive force-directed Steiner trees [16], non-Hanan routing [17], wire-sizing optimization [3], [6], [7], [11], [12], [27], =-=[31]-=-, as well as the more recent studies that combined topology construction with repeater insertion and/or wire sizing [18], [28], [29], [34] assumed RC models for the interconnects. With the exceptions ... |

7 | Two-pole analysis of interconnection trees
- Kahng, Muddu
- 1995
(Show Context)
Citation Context ...ff 1sj j! s j ∞ 0 t jhistsdt ∞ ∑ j 0sff 1sj m j i s j fi (1) where m ji is the j-th moment of the transfer function. Moments of an RLC interconnect can be computed by the methods proposed in =-=[20, 21]-=-. From the first 2q ff 1 moments, one can construct a q-pole transfer function ˆHisssto approximate the actual transfer function Hisssas follows: ˆHisssflsq ∑ j 1 k j s ff p j (2) where p j’s are ... |

6 |
Transmission line synthesis
- Krauter, Gupta, et al.
- 1995
(Show Context)
Citation Context ...signal settling time to be the time taken for the signal to settle above 90% of Vdd. Voltage overshoot (undershoot) is the maximum deviation over (under) the final voltage. Similar to [13], [14], and =-=[25]-=-, we use moments as an indirect metric to measure signal quality. For example, if we use the two-pole model in (2) to model the interconnect, then ringing can be attributed to the existence of complex... |

6 | Fast optimal algorithms for the minimum rectilinear Steiner arborescence problem
- Leung, Cong
- 1997
(Show Context)
Citation Context ...nly used topologies when we use the path-length delay formulation with tT(u; v) =dT(u; v). For example, by setting qi = d(s0;si) for all sinks, an optimal RATS tree is an optimal Steiner arborescence =-=[26]-=-. If we relax the requirement such that all sinks have the same required arrival time, then an optimal RATS tree is an optimal bounded-radius Steiner tree [4]. Lastly, an optimal RATS tree with unboun... |

6 |
On the bounded-skewrouting tree problem
- Huang, Kahng, et al.
- 1995
(Show Context)
Citation Context ...erging and the skipping (of merging) of subtrees at a Steiner merging point as in [26]. There are three significant differences. First, we consider the rerooting of a subtree (a concept introduced in =-=[19]-=-) at Hanan grid points. Second, [26] was purely based on path-length delay model; we consider a higher order RLC model. Third, we generate a set of topologies. Each node in the B&B search tree is asso... |

4 | Simultaneous buffer insertion and nonhanan optimization for VLSI interconnect under a higher order AWE model
- Hu, Sapatnekar
- 1999
(Show Context)
Citation Context ...n-Hanan routing [17], wire-sizing optimization [3], [6], [7], [11], [12], [27], [31], as well as the more recent studies that combined topology construction with repeater insertion and/or wire sizing =-=[18]-=-, [28], [29], [34] assumed RC models for the interconnects. With the exceptions of [12], [18], and [29], which considered higher order RC models, all other studies used the Elmore delay model [10], wh... |

3 | Pillage, “OTTER: Optimal termination of transmission lines excluding radiation
- Gupta, T
- 1994
(Show Context)
Citation Context ...efine the signal settling time to be the time taken for the signal to settle above 90% of Vdd. Voltage overshoot (undershoot) is the maximum deviation over (under) the final voltage. Similar to [13], =-=[14]-=-, and [25], we use moments as an indirect metric to measure signal quality. For example, if we use the two-pole model in (2) to model the interconnect, then ringing can be attributed to the existence ... |

3 | New performancedriven routing techniqueswith explicit area/delay tradeoff and simultaneous wire sizing - Lillis, Cheng, et al. - 1996 |

3 | Kahng and S Muddu. Two-pole analysis of interconnection trees - B - 1995 |

2 |
analytic delay model for RLC interconnects
- “An
- 1997
(Show Context)
Citation Context ... =tf (s0;si) + t(s0;si): (1) In this paper, we model the transition delay with a higher order moment-based delay model. More specifically, we use the two-pole-based analytical delay model proposed in =-=[21]-=- to approximate the time taken for a rising signal to reach 90% of Vdd for the first time at node i as follows: t(s0;si) where m j i m + 4m 03(m ) 2:36 1 1:66 1 2 ; if 4m 2 i 0 3 m 1 i 2 (m ) 0m 3(m )... |

1 | BufferedSteiner tree constructionwith wire sizing for interconnect layout optimization - Cong - 1996 |

1 | New performance driven routing techniqueswith explicit area/delay tradeoff and simultaneous wire sizing - Lillis, Cheng, et al. - 1996 |

1 |
A new layout-driven timing model for incremental layout optimization
- Liu, Lillis, et al.
- 1997
(Show Context)
Citation Context ...ing [17], wire-sizing optimization [3], [6], [7], [11], [12], [27], [31], as well as the more recent studies that combined topology construction with repeater insertion and/or wire sizing [18], [28], =-=[29]-=-, [34] assumed RC models for the interconnects. With the exceptions of [12], [18], and [29], which considered higher order RC models, all other studies used the Elmore delay model [10], which accounte... |

1 | Constrained multivariable optimization of transmission lines with general topologies
- Gupta, Pileggi
- 1995
(Show Context)
Citation Context ..., we define the signal settling time to be the time taken for the signal to settle above 90% of Vdd. Voltage overshoot (undershoot) is the maximum deviation over (under) the final voltage. Similar to =-=[13]-=-, [14], and [25], we use moments as an indirect metric to measure signal quality. For example, if we use the two-pole model in (2) to model the interconnect, then ringing can be attributed to the exis... |

1 |
High performance VLSI global routing
- Madden
- 1998
(Show Context)
Citation Context ...MINOTAUR Global Router The ability of the RATS-tree algorithm to generate a set of routing topologies for a timing-critical net complements a performance-driven MCM global router called MINOTAUR [8], =-=[30]-=-. Presented with a set of candidate routing topologies for each timing-critical net, the MINOTAUR global router has the flexibility to choose a topology from the set of candidate topologies of each ne... |