Interconnect Layout Optimization under Higher-Order RLC Model for MCM Designs

Interconnect Layout Optimization under Higher-Order RLC Model for MCM Designs (1997)

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by Jason Cong , Cheng-Kok Koh , Patrick H. Madden

Venue:	IN PROC. INT. CONF. ON COMPUTER AIDED DESIGN
Citations:	23 - 4 self

BibTeX

@INPROCEEDINGS{Cong97interconnectlayout,
    author = {Jason Cong and Cheng-Kok Koh and Patrick H. Madden},
    title = {Interconnect Layout Optimization under Higher-Order RLC Model for MCM Designs},
    booktitle = {IN PROC. INT. CONF. ON COMPUTER AIDED DESIGN},
    year = {1997},
    pages = {713--720},
    publisher = {}
}

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Abstract

Citations

2605	Graph-based algorithms for Boolean function manipulation - Bryant - 1986
320	The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers - Elmore - 1948
311	Asymptotic waveform evaluation for timing analysis - Pillage, Rohrer - 1990
128	On Steiner’s problem with rectilinear distance,” in Proc - Hanan - 1966
91	Optimal wire sizing and buffer insertion for low power and a generalized delay model - Lillis, Cheng, et al. - 1995
90	Performance optimization of VLSI interconnect layout - Cong, He, et al. - 1996
86	A new class of iterative steiner tree heuristics with good performance - Kahng, Robins - 1992
68	Provably good performance-driven global routing - Cong, Kahng, et al. - 1992
62	Performance-Driven Interconnect Design Based on Distributed RC Delay Model - Cong, Leung, et al. - 1993
48	Optimal wiresizing under the distributed Elmore delay model - Cong, Leung - 1995
47	Near-optimal critical sink routing tree constructions - Boese, Kahng, et al. - 1995
44	Timing models for MOS circuits - Horowitz - 1984
43	New Performance Driven Routing Techniques with Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing - Lillis, Cheng, et al. - 1996
37	An edge-based heuristic for Steiner routing - Borah, Owens, et al. - 1994
35	Optimal wiresizing formula under the Elmore delay model - Chen, Chen, et al. - 1996
31	An Analytical Delay Model for RLC Interconnects - Kahng, Muddu - 1997
30	Simultaneous routing and buffer insertion with restrictions on buffer locations - Zhou, Wong, et al. - 2000
27	Performance driven multi-layer general area routing for PCB/MCM designs - Cong, Madden - 1998
26	Performance-Driven Steiner Tree Algorithms for Global Routing - Hong, Xue, et al. - 1993
21	An E cient Multilayer MCM Router based on Four-via Routing - Khoo, Cong - 1995
21	Manhattan or nonManhattan? a study of alternative VLSI routing architectures - Koh, Madden - 2000
16	A sensitivity-based wiresizing approach to interconnect optimization of lossy transmission line topologies - Xue, Kuh, et al. - 1996
13	Shaping a VLSI wire to minimize Elmore delay - Fishburn - 1997
12	Exact MomentMatching Model of Transmission Lines and Application to Interconnect Delay Estimation - Yu, Kuh - 1995
10	Two-pole Analysis of Interconnection Trees - Kahng, Muddu - 1995
9	RC interconnect synthesis -- a moment fitting appraoch - Menezes, Pullela, et al. - 1994
9	High performance multichip interconnection design - Zhou, Tsui, et al. - 1993
8	Performance driven MCM Routing Using a Second Order RLC Tree Delay Model”, PTOC - Sriram, Kang - 1993
8	Non-Hanan routing - Hou, Hu, et al. - 1999
7	Shaping a VLSI wire to minimize delay using transmission line model - Gao, Wong - 1998
7	RC interconnect synthesis—a moment fitting approach - MENEZES, PULLELA, et al. - 1994
6	Transmission line synthesis - Krauter, Gupta, et al. - 1995
6	On the bounded-skew routing tree problem - HUANG, KAHNG, et al. - 1995
4	Fast Optimal Algorithms for the Minimum Rectilinear Steiner Arborescence Problem", UCLA Computer Science - Leung, Cong - 1996
4	Simultaneous buffer insertion and nonhanan optimization for VLSI interconnect under a higher order AWE model - Hu, Sapatnekar - 1999
3	New performancedriven routing techniqueswith explicit area/delay tradeoff and simultaneous wire sizing - Lillis, Cheng, et al. - 1996
2	Pillage, “OTTER: Optimal termination of transmission lines excluding radiation - Gupta, T - 1994
2	Kahng and S Muddu. Two-pole analysis of interconnection trees - B - 1995
1	BufferedSteiner tree constructionwith wire sizing for interconnect layout optimization - Cong - 1996
1	New performance driven routing techniqueswith explicit area/delay tradeoff and simultaneous wire sizing - Lillis, Cheng, et al. - 1996
1	A new layout-driven timing model for incremental layout optimization - Liu, Lillis, et al. - 1997
1	Constrained multivariable optimization of transmission lines with general topologies - Gupta, Pileggi - 1995
1	analytical delay model for RLC interconnects - “An - 1996
1	High performance VLSI global routing - Madden - 1998