@MISC{_usingc-to-hardware, author = {}, title = {USING C-TO-HARDWARE ACCELERATION IN FPGAS FOR WAVEFORM BASEBAND PROCESSING}, year = {} }
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Abstract
Software-defined radio (SDR) architectures typically include general-purpose CPUs (GPPs), digital signal processing (DSP) ASSPs and FPGAs that process different waveforms, functions, and algorithms. GPPs typically handle network protocol processing and management functions. Historically, DSPs handled transceiver baseband processing and encoding, while FPGAs provided highperformance IF up/down conversion and preconditioning functions. Now FPGAs, when used with embedded softcore processors, have absorbed the DSP baseband processing and some GPP functionality as well, providing a smaller, lower power solution. However, meeting the baseband performance requirements requires aggressive use of hardware acceleration. In this paper, we discuss an efficient methodology for hardware acceleration of SDR waveforms, the creation and use of hardware acceleration units, and a tool that automates the flow. The Altera ® Nios ® II C-to-Hardware (C2H) Acceleration Compiler is a coprocessor generation tool that converts performancecritical ANSI C functions into hardware accelerator modules with direct memory access. Results are presented showing performance gains of 13–73X over software only, offering a promising solution for rapid development of high-performance SDR systems. 1.