## A Statistical Circuit Optimization Algorithm under Thermal and Timing Constraints

### BibTeX

@MISC{Ling_astatistical,

author = {Tsui-yee Ling and I-jye Lin and Yao-wen Chang},

title = {A Statistical Circuit Optimization Algorithm under Thermal and Timing Constraints},

year = {}

}

### OpenURL

### Abstract

Process Variation has become a crucial challenge on both interconnect delay and reliability of nanometer integrated circuit designs. Furthermore, the dramatic increase of power consumption and integration density has led to high operating temperature. Temperature, as well as electromigration (EM) and power, also significantly affects the delay and reliability of interconnects. Considering process variation, we use statistical methods to simultaneously optimize the circuit area, delay, power, thermal, and EM reliability by sizing circuit components (both wires and gates). We model the problem as a second-order conic program and solve it with the interior-point optimization method. Experimental results show that our statistical algorithm can efficiently find desired solutions that satisfy all delay, power, and thermal constraints. 1

### Citations

9158 | Introduction to Algorithms - Cormen, Leiserson, et al. - 1998 |

4137 |
L.: Convex Optimization
- Boyd, Vandenberghe
- 2004
(Show Context)
Citation Context ... multiple parameter variations and the thermal issue using SOCP by sizing circuit components (wires and gates). The SOCP is convex and guarantees a globally optimal solution of the formulated problem =-=[5]-=-. Further, SOCP can be solved efficiently by interior point methods [18] with complexity close to O(N 1.3 ) in the size of the circuit, N. Because of these two important natures, we choose the SOCP fo... |

411 |
The Transient Response of Damped Linear Networks with Particular Regard to Wide Band Amplifiers
- Elmore
- 1948
(Show Context)
Citation Context ...re coefficient of resistance (1/ ◦ C), and T is the component temperature. In practice, interconnect resistance increases by 5% for every 10 ◦ C increase in temperature. For the Elmore RC delay model =-=[12]-=-, the resistance affects design performance directly. Due to the temperature increase in modern IC design, considering temperature-dependent resistance is getting more and more important. 3.2 Determin... |

90 | Fast and Exact Simultaneous Gate and Wire Sizing by Lagrangian Relaxation
- Chen, Chu, et al.
- 1998
(Show Context)
Citation Context ... is ĉixi, where ˆri and ĉi are the resistance and capacitance of gate i of unit-size, respectively. In addition, R D i is the resistance of the primary input driver i with 1 ≤ i ≤ s. However, same as =-=[8, 14]-=-, the intrinsic gate delay is ignored in this model for simplicity, since including intrinsic gate delay will not affect the technical contents of our work (and the previous works as well) but will ma... |

66 | Electromigration—A Brief Survey and Some Recent Results
- Black
- 1969
(Show Context)
Citation Context ...a and delay considering two major thermal effects on interconnect. 3.1.1 Influence of Self-Heating on EM The EM lifetime reliability of metal interconnects is governed by the wellknown Black equation =-=[4]-=-: TTF = A ⋆ · j −n · exp( Q kBTm ), (6)swhere TTF is the time-to-failure period, A ⋆ is a constant which is dependent on the geometry and microstructure of the interconnect, j is the DC or average cur... |

56 |
Cell-Level Placement for Improving Substrate Thermal Distribution
- Tsai, Kang
- 2000
(Show Context)
Citation Context ... effects may incur significant timing violations and fail in EM requirements in interconnects. Most previous works focus on reducing the maximum on-chip temperature during floorplanning and placement =-=[9, 23]-=-. While improving power, area, timing, and crosstalk by sizing circuit components have been extensively discussed in the recent literature [14], not much work has been addressed on thermal in the doma... |

43 | An efficient algorithm for statistical minimization of total power under timing yield constraints - Mani, Devgan, et al. |

36 |
Novel Sizing Algorithm for Yield Improvement Under Process Variation in Nanometer Technology
- Choi, Paul, et al.
- 2004
(Show Context)
Citation Context ...techniques instead of pessimistic worst-case values has become an inevitable trend. Gate sizing algorithms for the circuit minimization considering different parametric yield constraints are proposed =-=[10, 16]-=-. However, not much work targets on the statistical optimization of interconnect performance and reliability. Another determinant on the interconnect performance is thermal. Higher integration density... |

35 |
Statistical Analysis and Optimization for VLSI: Timing and Power
- Srivastava, Sylvester, et al.
- 2005
(Show Context)
Citation Context ... the variability of process parameters. It is predicted that the variability of interconnect parameters such as wire thickness and inter-layer dielectric (ILD) thickness will raise to 35% before 2007 =-=[22]-=-. However, traditional corner-model based analysis and optimization on the circuit performance are no longer acceptable as the magnitude of parameter variations becomes significant. The worst-case cor... |

25 | Partition-Driven Standard Cell Thermal Placement
- Chen, Sapatnekar
- 2003
(Show Context)
Citation Context ... effects may incur significant timing violations and fail in EM requirements in interconnects. Most previous works focus on reducing the maximum on-chip temperature during floorplanning and placement =-=[9, 23]-=-. While improving power, area, timing, and crosstalk by sizing circuit components have been extensively discussed in the recent literature [14], not much work has been addressed on thermal in the doma... |

25 | Crosstalk Driven Interconnect Optimization by Simultaneous Gate and Wire Sizing
- Jiang, Chang, et al.
- 2000
(Show Context)
Citation Context ...n-chip temperature during floorplanning and placement [9, 23]. While improving power, area, timing, and crosstalk by sizing circuit components have been extensively discussed in the recent literature =-=[14]-=-, not much work has been addressed on thermal in the domain of interconnect optimization. In this paper, we present the first work to optimize the interconnect performance considering the both impacts... |

21 | A new statistical optimization algorithm for gate sizing
- Mani, Orshansky
- 2004
(Show Context)
Citation Context ...techniques instead of pessimistic worst-case values has become an inevitable trend. Gate sizing algorithms for the circuit minimization considering different parametric yield constraints are proposed =-=[10, 16]-=-. However, not much work targets on the statistical optimization of interconnect performance and reliability. Another determinant on the interconnect performance is thermal. Higher integration density... |

15 |
On thermal effects
- Banerjee, Mehrotra, et al.
- 1999
(Show Context)
Citation Context ...ensity, n is typically 2, Q is the activation energy for grainboundary diffusion and equals 0.7eV for Al-Cu, kB is the Boltzmann constant, and Tm is the metal temperature. Moreover, by previous works =-=[2, 3]-=-, maintaining the following equation can guarantee the EM reliability lifetime: exp � � Q kBTm j2 � � Q exp kBTref ≥ . (7) avg Under the specific current density, j0, and metal temperature, Tref , the... |

13 |
The impact of device parameter variation on the frequency and performance of VLSI chips
- Samaan
- 2004
(Show Context)
Citation Context ...uency was set to 3 GHz. Both the variability in ILD thickness and the variability in wire thickness are explored 10% of σ/µ. Since the data on spatial correlation is usually not available, and Samaan =-=[20]-=- pointed out that the spatially correlated components are not numerically significant, we do not consider the spatial correlation. We used a set of RC parameters based on the 0.18 µm technology. The v... |

8 |
A.H.: Analysis and Optimization of Thermal Issues
- Banerjee, Pedram, et al.
- 2001
(Show Context)
Citation Context ... thermal. Higher integration density and rising power consumption lead to higher temperature in modern VLSI circuits. Thermal greatly affects interconnect design and electromigration (EM) reliability =-=[3]-=-. For nanometer high-performance circuits, ignoring thermal effects may incur significant timing violations and fail in EM requirements in interconnects. Most previous works focus on reducing the maxi... |

5 | Noise-constrained performance optimization by simultaneous gate and wire sizing based on lagrangian relaxation - Jiang, Jou, et al. - 1999 |

4 |
Multilevel Metal Capacitance Models for
- Chern, Huang, et al.
- 1992
(Show Context)
Citation Context ...om deviations of T and H. a1, b1, b2 are T to R, T to C, H to C sensitivities which can be obtained by running SPICE empirically or applying the differential differentiation of the following equations=-=[7]-=-: R = ρ WT , Cgnd ǫ = W H � T + 3.28 T + 2H �0.023 � + S S + 2H �1.16 , where Cgnd/ǫ is the normalized capacitance, and S is the clear space between parallel lines. In this paper, we adopt the differe... |

3 | Boundary Value Problems of Heat Condition - Ozisik - 1968 |

1 |
Variational Dela Metrics for Interconnect Timing Analysis
- Agarwal, Sylvester, et al.
- 2004
(Show Context)
Citation Context ...nnect delay, the average temperature of the circuit, and EM reliability by a deterministic formulation. To guide our statistical optimization on interconnect, we adopt the RC delay variation model in =-=[1]-=-, which has the variability of wire thickness and ILD thickness as the variation sources, for our statistical problem formulation. The statistical optimization problem with wire sizing alone can be re... |