DMCA
Low-Power CMOS Digital Design (1992)
| Venue: | JOURNAL OF SOLID-STATE CIRCUITS. VOL 27, NO 4. APRIL 1992 413 |
| Citations: | 568 - 20 self |
BibTeX
@MISC{Chandrakasan92low-powercmos,
author = {Anantha P. Chandrakasan and Samuel Sheng and Robert W. Brodersen},
title = { Low-Power CMOS Digital Design},
year = {1992}
}
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Abstract
Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low-power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. An architectural-based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations. This optimum is achieved by trading increased silicon area for reduced power consumption.
Keyphrases
low-power cmos digital design computational throughput logic style technology optimization possible supply voltage architectural-based scaling strategy portable environment optimum voltage cmos digital circuit power consumption battery-operated application reduced power consumption demand intensive computation silicon area
