## Equivalent Elmore Delay for RLC Trees (2000)

### Cached

### Download Links

Venue: | Proceedings of the ACM/IEEE Design Automation Conference |

Citations: | 30 - 8 self |

### BibTeX

@ARTICLE{Ismail00equivalentelmore,

author = {Yehea I. Ismail and Eby G. Friedman and José L. Neves},

title = {Equivalent Elmore Delay for RLC Trees},

journal = {Proceedings of the ACM/IEEE Design Automation Conference},

year = {2000},

volume = {19},

pages = {83--97}

}

### OpenURL

### Abstract

Abstract—Closed-form solutions for the 50 % delay, rise time, overshoots, and settling time of signals in an tree are presented. These solutions have the same accuracy characteristics of the Elmore delay for trees and preserves the simplicity and recursive characteristics of the Elmore delay. Specifically, the complexity of calculating the time domain responses at all the nodes of an tree is linearly proportional to the number of branches in the tree and the solutions are always stable. The closed-form expressions introduced here consider all damping conditions of an circuit including the underdamped response, which is not considered by the Elmore delay due to the nonmonotone nature of the response. The continuous analytical nature of the solutions makes these expressions suitable for design methodologies and optimization techniques. Also, the solutions have significantly improved accuracy as compared to the Elmore delay for an overdamped response. The solutions introduced here for trees can be practically used for the same purposes that the Elmore delay is used for trees.

### Citations

402 |
Digital Integrated Circuits : A Design Perspective
- Rabaey
- 2003
(Show Context)
Citation Context ... for the same purposes that the Elmore delay is used for RC trees. I. Introduction It has become well accepted that interconnect delay dominates gate delay in current deep submicrometer VLSI circuits =-=[1]-=--[9]. With the continuous scaling of technology and increased die area, this situation is becoming worse. In order to properly design complex circuits, more accurate interconnect models and signal pro... |

385 |
Asymptotic Waveform Evaluation for Timing Analysis
- Pillage, Rohrer
- 1990
(Show Context)
Citation Context ...nsfer function [33]. The first 2q moments of the transfer function include the information needed to calculate the first q poles and the residues of these poles. Numerical methods have been developed =-=[34]-=--[37] to efficiently calculate the moments, poles, and residues. Also, model order reduction techniques based on the state space representation of an RLC network have been used to calculate the transi... |

366 |
The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers
- Elmore
- 1948
(Show Context)
Citation Context ...e process of characterizing signal waveforms in tree structured interconnect is of primary importance. One of the more popular delay models used within industry for RC trees is the Elmore delay model =-=[15]-=-, [16]. Despite not being highly accurate, the Elmore delay is widely used by industry for fast delay estimation. With IC's composed of tens of millions of gates it is often impractical to use highly ... |

284 |
passive reducedorder interconnect macromodeling algorithm
- Odabasioglu, Celik, et al.
- 1997
(Show Context)
Citation Context ...mple ‚vg circuit. via lanczos (PVL) [38], matrix pade via lanczos (MPVL) [39], arnoldi algorithm [40], block arnoldi algorithm [41], passive reduced-order interconnect macromodeling algorithm (PRIMA) =-=[42]-=-, [43], and SyPVL Algorithm [44]. However, the Elmore (Wyatt) delay is still widely used within industry since it is computationally faster to evaluate and always leads to stable solutions. Also, due ... |

239 |
SPICE2: A Computer Program to Simulate Semiconductor Circuits
- Nagel
- 1975
(Show Context)
Citation Context ... has a high degree of fidelity [17]: an optimal or near-optimal solution achieved by a design methodology based on the Elmore delay is also near-optimal based on a more accurate (e.g., SPICE-computed =-=[24]-=-) delay for routing constructions [25] and wire sizing optimization [23]. Simulations [26] have shown that the clock skew derived under the Elmore delay model has a high correlation with SPICE-derived... |

219 | Efficient linear circuit analysis by Padé approximation via the Lanczos process
- Feldmann, RW
- 1995
(Show Context)
Citation Context ...odel order reduction techniques based on the state space representation of an RLC network have been used to calculate the transient response of signals within the tree such as: Pade via Lanczos (PVL) =-=[38]-=-, Matrix Pade via Lanczos (MPVL) [39], Arnoldi Algorithm [40], Block Arnoldi Algorithm [41], Passive Reduced-Order Interconnect Macromodeling Algorithm (PRIMA) [42], [43], and SyPVL Algorithm [44] whi... |

180 | Signal delay in RC tree networks
- Rubinstein, eld, et al.
- 1983
(Show Context)
Citation Context ...derived under the Elmore delay model has a high correlation with SPICE-derived skew data. The popularity of the Elmore delay is mainly due to the existence of a simple tractable formula for the delay =-=[29]-=- that has recursive properties [27], making the calculation of the circuit delays highly efficient even in large circuits. No formula for delay calculation has been determined for RLC trees that maint... |

81 |
Ginneken, Buffer Placement In Distributed RG Tree Networks for Minimal Elmore Delay
- van
- 1990
(Show Context)
Citation Context ...l has a high correlation with SPICE-derived skew data. The popularity of the Elmore delay is mainly due to the existence of a simple tractable formula for the delay [29] that has recursive properties =-=[27]-=-, making the calculation of the circuit delays highly efficient even in large circuits. No formula for delay calculation has been determined for trees that maintains all the characteristics of the Elm... |

75 | Figures of Merit to Characterize the Importance of On-Chip Inductance”, DAC’98 - Ismail, Friedman, et al. - 1998 |

74 | Wire Segmenting for Improved Buffer Insertion
- Alpert, Devgan
- 1997
(Show Context)
Citation Context ...ions to be performed for only the critical paths. Also, the Elmore delay is widely used as a delay model for the 2 synthesis of VLSI circuits such as buffer insertion in RC trees and wire sizing [17]-=-=[28]-=-. The wide use of the Elmore delay as a basis for design methodologies is primarily because the Elmore delay has a high degree of fidelity [17]: an optimal or near-optimal solution achieved by a desig... |

71 |
Approximation of Wiring Delay in MOSFET LSI
- Sakurai
- 1983
(Show Context)
Citation Context ...e lumped capacitance in the analysis of the performance of on-chip interconnects. Currently, RC models are used for high resistance nets and capacitive models are used for less resistive interconnect =-=[10]-=-, [11]. However, inductance is becoming more important with faster on-chip rise times and longer wire lengths. Wide wires are frequently encountered in clock distribution networks and in upper metal l... |

67 | Reduced-order modeling of large linear subcircuits via a block Lanczos algorithm
- Feldmann, Freund
- 1995
(Show Context)
Citation Context ... on the state space representation of an RLC network have been used to calculate the transient response of signals within the tree such as: Pade via Lanczos (PVL) [38], Matrix Pade via Lanczos (MPVL) =-=[39]-=-, Arnoldi Algorithm [40], Block Arnoldi Algorithm [41], Passive Reduced-Order Interconnect Macromodeling Algorithm (PRIMA) [42], [43], and SyPVL Algorithm [44] which exploits the natural symmetry of t... |

53 |
Electronic circuit and system simulation methods
- Pillage, Rohrer, et al.
- 1995
(Show Context)
Citation Context ...sfer function by matching boundary conditions [32]. Pillage extended this concept by introducing asymptotic wave evaluation (AWE), which depends on matching the first moments of the transfer function =-=[33]-=-–[35] rather than only the first moment as Wyatt and Elmore did. This concept allows arbitrary accuracy by including additional moments. The normalized transfer function can be expanded in the powers ... |

52 | Efficient ReducedOrder Modeling of Frequency-Dependent Coupling Inductance Associated with
- Silveria, Kamon, et al.
- 1995
(Show Context)
Citation Context ...esentation of an RLC network have been used to calculate the transient response of signals within the tree such as: Pade via Lanczos (PVL) [38], Matrix Pade via Lanczos (MPVL) [39], Arnoldi Algorithm =-=[40]-=-, Block Arnoldi Algorithm [41], Passive Reduced-Order Interconnect Macromodeling Algorithm (PRIMA) [42], [43], and SyPVL Algorithm [44] which exploits the natural symmetry of the model order reduction... |

50 | Simultaneous driver and wire sizing for performance and power optimization - Cong, Koh - 1994 |

46 | RC interconnect optimization under the Elmore delay model - Sapatnekar - 1994 |

43 | Krylov space methods on state-space control models, Circuits Syst
- Boley
- 1994
(Show Context)
Citation Context ...ave been used to calculate the transient response of signals within the tree such as: Pade via Lanczos (PVL) [38], Matrix Pade via Lanczos (MPVL) [39], Arnoldi Algorithm [40], Block Arnoldi Algorithm =-=[41]-=-, Passive Reduced-Order Interconnect Macromodeling Algorithm (PRIMA) [42], [43], and SyPVL Algorithm [44] which exploits the natural symmetry of the model order reduction problems. However, the Elmore... |

42 | Reduced-order modeling of large passive linear circuits by means of the sypvl algorithm
- Freund, Feldmann
- 1996
(Show Context)
Citation Context ...VL) [38], Matrix Pade via Lanczos (MPVL) [39], Arnoldi Algorithm [40], Block Arnoldi Algorithm [41], Passive Reduced-Order Interconnect Macromodeling Algorithm (PRIMA) [42], [43], and SyPVL Algorithm =-=[44]-=- which exploits the natural symmetry of the model order reduction problems. However, the Elmore (Wyatt) delay is still widely used within industry since it is computationally faster to evaluate and al... |

38 | High-performance routing trees with identified critical sinks - Boese, Kahng, et al. - 1993 |

37 | An analytical delay model for RLC interconnects
- Kahng, Muddu
- 1996
(Show Context)
Citation Context ...absence of an equivalent delay model for RLC trees is primarily due to the fact that the Elmore delay does not cover non-monotone responses [15] which can occur in RLC circuits. The work described in =-=[30]-=- uses the first and second moments to characterize the response of RLC trees. However, the solutions in [30] are composed of three different formulae for the cases of real, complex, and multiple poles... |

36 |
Designing the Best Clock Distribution Network
- Restle, Deutsch
- 1998
(Show Context)
Citation Context ...equirements are pushing the introduction of new materials for low resistance interconnect [12]. Inductance is therefore becoming an integral element in VLSI design methodologies, see e.g., [6], [13], =-=[14]-=-. An interconnect line in a VLSI circuit is in general a tree rather than a single line. Thus, the process of characterizing signal waveforms in tree structured interconnect is of primary importance. ... |

34 |
rapid interconnect circuit evaluator
- Ratzlaff, Gopal, et al.
- 1991
(Show Context)
Citation Context ...function by matching boundary conditions [32]. Pillage extended this concept by introducing asymptotic wave evaluation (AWE), which depends on matching the first moments of the transfer function [33]–=-=[35]-=- rather than only the first moment as Wyatt and Elmore did. This concept allows arbitrary accuracy by including additional moments. The normalized transfer function can be expanded in the powers of as... |

33 | Fidelity and Near-Optimality of Elmore-Based Routing Constructions
- Boese, Kahng, et al.
- 1993
(Show Context)
Citation Context ...n optimal or near-optimal solution achieved by a design methodology based on the Elmore delay is also near-optimal based on a more accurate (e.g., SPICE-computed [24]) delay for routing constructions =-=[25]-=- and wire sizing optimization [23]. Simulations [26] have shown that the clock skew derived under the Elmore delay model has a high correlation with SPICE-derived skew data. The popularity of the Elmo... |

33 | Inductance on Silicon for Sub-Micron CMOS - Priore - 1993 |

30 | High-speed VLSI interconnect modeling based on Sparameter measurements - Eo, Eisenstadt - 1993 |

27 |
FD-TD Modeling of Digital Signal Propagation in 3-D Circuits with Passive and Active Loads
- May, Taflove, et al.
- 1994
(Show Context)
Citation Context ... the same purposes that the Elmore delay is used for RC trees. I. Introduction It has become well accepted that interconnect delay dominates gate delay in current deep submicrometer VLSI circuits [1]-=-=[9]-=-. With the continuous scaling of technology and increased die area, this situation is becoming worse. In order to properly design complex circuits, more accurate interconnect models and signal propaga... |

27 |
Ginneken, "Buffer placement in distributed RC-tree networks for minimal Elmore delay
- van
- 1990
(Show Context)
Citation Context ...l has a high correlation with SPICE-derived skew data. The popularity of the Elmore delay is mainly due to the existence of a simple tractable formula for the delay [29] that has recursive properties =-=[27]-=-, making the calculation of the circuit delays highly efficient even in large circuits. No formula for delay calculation has been determined for RLC trees that maintains all the characteristics of the... |

24 | Inductance on Silicon for Sub-Micron CMOS VLSI - Priore - 1993 |

21 | G.Robins, “Rectilinear Steiner Trees with Minimum Elmore - Boese, McCoy - 1994 |

20 | The Effects of Interconnections on HighSpeed Logic Circuits - Jarvis - 1963 |

20 | When are transmission-line effects important for on-chip interconnections - Deutsch - 1997 |

20 |
Advanced Copper Interconnections for Silicon CMOS
- Torres
- 1995
(Show Context)
Citation Context ...These wires are low resistive wires that can exhibit significant inductive effects. Furthermore, performance requirements are pushing the introduction of new materials for low resistance interconnect =-=[12]-=-. Inductance is therefore becoming an integral element in VLSI design methodologies, see e.g., [6], [13], [14]. An interconnect line in a VLSI circuit is in general a tree rather than a single line. T... |

20 | Accurate analytical delay models for VLSI interconnects
- Kahng, Muddu
- 1996
(Show Context)
Citation Context ...thesis and VLSI-oriented design methodologies. Asymptotic wave evaluation is mainly used in analyzing those networks that require high accuracy and covers both monotone and non-monotone responses. In =-=[45]-=-, the first and second moments are used to evaluate the delay of a VLSI interconnect. However, no closed form solution is described for RLC trees. 6 III. Second Order Approximation for RLC Trees As me... |

19 | Analysis of high-speed VLSI interconnect using the symptotic waveform evaluation technique - Tang, Nakhla - 1992 |

15 | Bounded-Skew Clock and Steiner Routing Under Elmore Delay
- Cong, Kahng, et al.
- 1995
(Show Context)
Citation Context ...ign methodology based on the Elmore delay is also near-optimal based on a more accurate (e.g., SPICE-computed [24]) delay for routing constructions [25] and wire sizing optimization [23]. Simulations =-=[26]-=- have shown that the clock skew derived under the Elmore delay model has a high correlation with SPICE-derived skew data. The popularity of the Elmore delay is mainly due to the existence of a simple ... |

14 | High-Speed Signal Propagation on lossy transmission lines - Deutsch - 1990 |

14 |
A System for Critical Path Analysis Based on Back Annotation and Distributed Interconnect Impedance Models
- Yacoub, Pham, et al.
- 1988
(Show Context)
Citation Context ...ed capacitance in the analysis of the performance of on-chip interconnects. Currently, RC models are used for high resistance nets and capacitive models are used for less resistive interconnect [10], =-=[11]-=-. However, inductance is becoming more important with faster on-chip rise times and longer wire lengths. Wide wires are frequently encountered in clock distribution networks and in upper metal layers.... |

14 |
Circuit Analysis, Simulation and Design
- Wyatt
- 1987
(Show Context)
Citation Context ...ess of characterizing signal waveforms in tree structured interconnect is of primary importance. One of the more popular delay models used within industry for RC trees is the Elmore delay model [15], =-=[16]-=-. Despite not being highly accurate, the Elmore delay is widely used by industry for fast delay estimation. With IC's composed of tens of millions of gates it is often impractical to use highly accura... |

13 |
Modeling and Characterization of Long Interconnections for High-Performance Microprocessors
- Deutsch
- 1995
(Show Context)
Citation Context ...rformance requirements are pushing the introduction of new materials for low resistance interconnect [12]. Inductance is therefore becoming an integral element in VLSI design methodologies, see e.g., =-=[6]-=-, [13], [14]. An interconnect line in a VLSI circuit is in general a tree rather than a single line. Thus, the process of characterizing signal waveforms in tree structured interconnect is of primary ... |

13 |
modeling of large linear subcircuits via a block Lanczos algorithm
- “Reduced-order
- 1995
(Show Context)
Citation Context ...esentation of an network have been used to calculate the transient response of signals within the tree such as: pade Fig. 4. Simple ‚vg circuit. via lanczos (PVL) [38], matrix pade via lanczos (MPVL) =-=[39]-=-, arnoldi algorithm [40], block arnoldi algorithm [41], passive reduced-order interconnect macromodeling algorithm (PRIMA) [42], [43], and SyPVL Algorithm [44]. However, the Elmore (Wyatt) delay is st... |

12 |
Pillage, "RICE: Rapid Interconnect Circuit Evaluator
- Ratzlaff, Gopal, et al.
- 1991
(Show Context)
Citation Context ...fer function by matching boundary conditions [32]. Pillage extended this concept by introducing asymptotic wave evaluation, which depends on matching the first q moments of the transfer function [33]-=-=[35]-=- rather than only the first moment as Wyatt and Elmore did. This concept allows arbitrary accuracy by including additional moments. The normalized transfer function g(s) can be expanded in the powers ... |

12 |
Coping with RC(L) interconnect design headaches
- Pillage
- 1995
(Show Context)
Citation Context ... function [33]. The first 2q moments of the transfer function include the information needed to calculate the first q poles and the residues of these poles. Numerical methods have been developed [34]-=-=[37]-=- to efficiently calculate the moments, poles, and residues. Also, model order reduction techniques based on the state space representation of an RLC network have been used to calculate the transient r... |

11 |
Delay evaluation with lumped linear RLC interconnect circuit models
- Pillage, Rohrer
- 1989
(Show Context)
Citation Context ... first order approximation of the transfer function can be inaccurate in certain cases where arbitrary initial conditions can create a low frequency zero, thereby violating one of Wyatt's assumptions =-=[31]-=-. For this reason, Horowitz approximates the capacitor voltage with a two pole one zero transfer function by matching boundary conditions [32]. Pillage extended this concept by introducing asymptotic ... |

8 |
Optimal wire sizing for interconnects with multiple sources
- Cong, He
- 1996
(Show Context)
Citation Context ... achieved by a design methodology based on the Elmore delay is also near-optimal based on a more accurate (e.g., SPICE-computed [24]) delay for routing constructions [25] and wire sizing optimization =-=[23]-=-. Simulations [26] have shown that the clock skew derived under the Elmore delay model has a high correlation with SPICE-derived skew data. The popularity of the Elmore delay is mainly due to the exis... |

8 | Performance Optimization of VLSI - Cong, He, et al. - 1996 |

7 |
A fast algorithm for computing the time moments of RLC circuits
- Ratzlaff
- 1991
(Show Context)
Citation Context ... R k and L K . For example, in Fig. 5, T RC7 = R 1 (C 1 +C 2 +...+C 7 ) + R 6 (C 3 +C 6 +C 7 ) + R 7 C 7 . This form of expressing the summations is convenient since it has recursive properties [29], =-=[48]-=-. The summations in (52) and (53) of a tree rooted at section w 1 are calculated in two steps. The first step is to calculate the total load capacitance seen by each section. A pseudo-code that perfor... |

6 |
Automatic Control Systems, A Design Perspective
- Kuo
- 1989
(Show Context)
Citation Context ...s defined as the time when the oscillations about the steady state are smaller than x of the steady state value. This parameter is usually called the settling time and x is typically chosen to be 0.1 =-=[47]-=-. The value of the maximum or minimum oscillations can be found by differentiating (31) with respect to time and equating the result to zero. The values for the maximum or minimum oscillations at node... |

5 | Performance optimization of VLSI interconnect
- Cong, He, et al.
- 1996
(Show Context)
Citation Context ...mulations to be performed for only the critical paths. Also, the Elmore delay is widely used as a delay model for the 2 synthesis of VLSI circuits such as buffer insertion in RC trees and wire sizing =-=[17]-=--[28]. The wide use of the Elmore delay as a basis for design methodologies is primarily because the Elmore delay has a high degree of fidelity [17]: an optimal or near-optimal solution achieved by a ... |

5 | Optimal wire sizing under the distributed Elmore delay model - Cong, Leung - 1993 |

5 |
et al, “A 400-MHz s/390 Microprocessor
- Webb
- 1997
(Show Context)
Citation Context ...nce requirements are pushing the introduction of new materials for low-resistance interconnect [12]. Inductance is therefore becoming an integral element in VLSI design methodologies, see, e.g., [6], =-=[13]-=-, and [14]. Manuscript received December 1, 1998; revised May 4, 1999. This work was supported in part by the National Science Foundation (NSF) under Grant MIP9610108, the Semiconductor Research Corpo... |