## Mapping for Better Than Worst-Case Delays In LUT-Based FPGA Designs (2008)

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Venue: | FPGA'08 |

Citations: | 3 - 0 self |

### BibTeX

@MISC{Cong08mappingfor,

author = {Jason Cong and Kirill Minkovich},

title = {Mapping for Better Than Worst-Case Delays In LUT-Based FPGA Designs},

year = {2008}

}

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### Abstract

Current advances in chip design and manufacturing have allowed IC manufacturing to approach the nanometer range. As the feature size scales down, greater variability is experienced, forcing designers to reduce performance requirements in order to reserve larger margins. Better than worst-case design can be used to address the variability problem, as well as breaking the performance limit set by the worst-case delay in the conventional design style, even without the consideration of delay variation. In this paper we will present a novel methodology for measuring and optimizing the performance of circuits to operate with the clock period smaller than the worst-case delay. We also develop a novel technology mapping algorithm that optimizes circuits under such a metric. Using our novel mapping algorithm named BTWMap (Better Than Worst-case Mapper) and its area-optimized version named BTWMap+area, we are able to improve the overall circuit latency by 13 % and 11%, respectively.

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Citation Context ...ich enables better trade-off between the area and the expected delay. BTWMap+area considers both the target clock period and the maximum mapping depth (which can be computed easily, say using FlowMap =-=[7]-=-, or in our cut enumeration framework [9]). For example, if the circuit has a maximum depth of 10 and a target clock period of 7 is specified, the algorithm will try to make sure the outputs will not ... |

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Citation Context ...ing mapping solution. 3. BTWMap BTWMap was created to optimize the logic for an FPGA using the cut-based approach, which was first used in ZMap [8] and later adopted in DAOMap [6], IMap [13], and ABC =-=[16]-=-. To perform this type of logic optimization, a set of cuts, or possible implementations, is first generated for each node. Then, the algorithm assigns a cost to each cut and recursively selects the b... |

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Citation Context ...abilities of inputs is very difficult. To overcome these difficulties, BTWMap uses a simulation-based method with several custom speedups. The BTWMap algorithm, based on the cut-enumeration framework =-=[9]-=-[16], will be presented in two parts. First, we will present our cost function and describe how it is used (Section 3.1). Then we will present several area/performance tradeoffs specifically designed ... |

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Citation Context ...plex notion of measuring delay on a delay error-resistant architecture, one first has to understand a simpler notion of propagation delay. For simplicity, as in most of other technology mapping works =-=[6]-=-[8], we use the unit delay model (prior to placement and routing). However, our technique can be extended to post-placement optimization with more accurate gate delay models. Under the unit delay mode... |

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1 |
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Citation Context ...the corresponding mapping solution. 3. BTWMap BTWMap was created to optimize the logic for an FPGA using the cut-based approach, which was first used in ZMap [8] and later adopted in DAOMap [6], IMap =-=[13]-=-, and ABC [16]. To perform this type of logic optimization, a set of cuts, or possible implementations, is first generated for each node. Then, the algorithm assigns a cost to each cut and recursively... |