## Digital Circuit Optimization via Geometric Programming (2005)

Venue: | Operations Research |

Citations: | 29 - 7 self |

### BibTeX

@ARTICLE{Boyd05digitalcircuit,

author = {Stephen P. Boyd and Seung-jean Kim and Dinesh D. Patil and Mark A. Horowitz},

title = {Digital Circuit Optimization via Geometric Programming},

journal = {Operations Research},

year = {2005},

volume = {53},

pages = {899--932}

}

### Years of Citing Articles

### OpenURL

### Abstract

informs ® doi 10.1287/opre.1050.0254 © 2005 INFORMS This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently solved. We start with a basic gate scaling problem, with delay modeled as a simple resistor-capacitor (RC) time constant, and then add various layers of complexity and modeling accuracy, such as accounting for differing signal fall and rise times, and the effects of signal transition times. We then consider more complex formulations such as robust design over corners, multimode design, statistical design, and problems in which threshold and power supply voltage are also variables to be chosen. Finally, we look at the detailed design of gates and interconnect wires, again using a formulation that is compatible with GP or GGP.

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Citation Context ...ion in delay of around 2.3%. These sensitivities are extremely useful since they quantify how ‘binding’ the power and area constraints are. (For more discussion of optimal sensitivities, see [19] and =-=[20]-=-.) 2.1.8 Other constraints There are many other constraints, compatible with geometric programming, that can be added. For example we can impose a maximum on the scale factors, xi ≤ xmax i , or we can... |

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Citation Context ...g) of a new solution method for each new problem formulation. In the mid 1990s interior-point algorithms for GP were developed, which can solve even large-scale GPs extremely efficiently and reliably =-=[20, 103, 105, 147]-=-. This opens the possibility of formulating even large circuit sizing problems as large-scale GPs, and directly solving them using interior-point methods. This approach easily handles complex problem ... |

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Citation Context ...ements); for more complex problem formulations it can also be done in a coordinated manner described in §2.5. For general background on digital circuit design, we refer the reader to the recent books =-=[143, 116, 63]-=-, which describe the sizing problem, and its context, in detail. The influential book [135] by Sproull, Sutherland, and Harris, is almost entirely devoted to the sizing problem. Sizing of digital circ... |

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Citation Context ...the main topics of this paper) can be found in, e.g., [36, 109, 38, 77, 98, 111, 111, 129, 123, 125, 126]. These are all based on gate delay models that are compatible with geometric programming; see =-=[77, 121, 135, 120, 1]-=- for more on such models. Work on interconnect sizing (also addressed in this paper) includes [4, 39, 41, 40, 42, 43, 32, 30, 54, 79, 89, 90, 124]; simultaneous gate and wire sizing is considered in [... |

165 |
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Citation Context ...roull, Sutherland, and Harris, is almost entirely devoted to the sizing problem. Sizing of digital circuits is a well researched field, with hundreds of papers on the topic; 2ssee, e.g., the articles =-=[52, 109, 32, 83, 77, 124, 126]-=- and the references therein. 1.2 Sizing optimization via geometric programming In this paper we focus on a particular approach, in which the sizing problem is modeled (at least approximately) as a geo... |

159 | Power minimization in IC design: Principles and applications
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Citation Context ...otal power is P = Pdyn + Pstat, 10swhich is a linear function of the scale factors, with positive coefficients, and therefore a posynomial. (For more details on dynamic and static power modeling, see =-=[25, 112, 119]-=-.) For the moment, we are assuming that power supply voltage and clock frequency (which scales the activity frequencies, assuming given activity factors) are constant. But if clock frequency or supply... |

153 |
Logical Effort: Designing Fast CMOS Circuits
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(Show Context)
Citation Context ... in §2.5. For general background on digital circuit design, we refer the reader to the recent books [143, 116, 63], which describe the sizing problem, and its context, in detail. The influential book =-=[135]-=- by Sproull, Sutherland, and Harris, is almost entirely devoted to the sizing problem. Sizing of digital circuits is a well researched field, with hundreds of papers on the topic; 2ssee, e.g., the art... |

132 |
Clustered voltage scaling technique for low-power design
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Citation Context ...sing the monomial inequality constraints Vdd,i ≥ Vdd,j for all j ∈ FO(i), which require that all gates only drive gates with smaller (or equal) supply voltage. This was proposed by Usami and Horowitz =-=[139]-=-, who called it clustered voltage scaling. We can also add a regularization term of the form λ n� � Vdd,i i=1 Vdd,j j∈FO(i) to the objective, which acts as a heuristic for enforcing a small number of ... |

121 | Energy minimization using multiple supply voltages
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Citation Context ... current research; see, e.g., [7, 24, 28, 74, 108, 134]. Many 34sapproaches to low power CMOS design have been proposed in the literature, including design with multiple supply and threshold voltages =-=[26, 71, 81, 82, 86, 97, 131, 134, 148]-=-, multiple threshold CMOS (MTCMOS) [6, 7, 23, 75], variable threshold CMOS (VTCMOS) via adaptive body biasing [66, 74, 138, 145], dynamic threshold CMOS (DTCMOS) [9], joint device sizing and Vdd/Vth a... |

115 |
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Citation Context ...otal power is P = Pdyn + Pstat, 10swhich is a linear function of the scale factors, with positive coefficients, and therefore a posynomial. (For more details on dynamic and static power modeling, see =-=[25, 112, 119]-=-.) For the moment, we are assuming that power supply voltage and clock frequency (which scales the activity frequencies, assuming given activity factors) are constant. But if clock frequency or supply... |

102 |
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Citation Context ...otal power is P = Pdyn + Pstat, 10swhich is a linear function of the scale factors, with positive coefficients, and therefore a posynomial. (For more details on dynamic and static power modeling, see =-=[25, 112, 119]-=-.) For the moment, we are assuming that power supply voltage and clock frequency (which scales the activity frequencies, assuming given activity factors) are constant. But if clock frequency or supply... |

102 | Performance optimization of VLSI interconnect layout
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(Show Context)
Citation Context ... all based on gate delay models that are compatible with geometric programming; see [77, 121, 135, 120, 1] for more on such models. Work on interconnect sizing (also addressed in this paper) includes =-=[4, 39, 41, 40, 42, 43, 32, 30, 54, 79, 89, 90, 124]-=-; simultaneous gate and wire sizing is considered in [29, 69]. In some of these papers, the authors develop custom methods for solving the resulting GPs, instead of using general purpose interior-poin... |

90 | An exact solution to the transistor sizing problem for CMOS circuits using convex optimization
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Citation Context ...roull, Sutherland, and Harris, is almost entirely devoted to the sizing problem. Sizing of digital circuits is a well researched field, with hundreds of papers on the topic; 2ssee, e.g., the articles =-=[52, 109, 32, 83, 77, 124, 126]-=- and the references therein. 1.2 Sizing optimization via geometric programming In this paper we focus on a particular approach, in which the sizing problem is modeled (at least approximately) as a geo... |

81 | D.F.: Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
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Citation Context ...] for more on such models. Work on interconnect sizing (also addressed in this paper) includes [4, 39, 41, 40, 42, 43, 32, 30, 54, 79, 89, 90, 124]; simultaneous gate and wire sizing is considered in =-=[29, 69]-=-. In some of these papers, the authors develop custom methods for solving the resulting GPs, instead of using general purpose interior-point methods (see, e.g., [36, 68, 149]). For some simple problem... |

74 | A general probabilistic framework for worst case timing analysis
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(Show Context)
Citation Context ...erformance specifications. The formulation (12) is a stochastic optimization problem. The statistical analysis and design of digital circuits is an area of growing interest and importance; see, e.g., =-=[2, 14, 21, 72, 106, 107]-=-. This is still an active research area, and no consensus has emerged as to what the best statistical models are. In the following sections, we base our development on some simple models that have bee... |

71 |
Approximation of Wiring Delay in MOSFET LSI
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(Show Context)
Citation Context ...the main topics of this paper) can be found in, e.g., [36, 109, 38, 77, 98, 111, 111, 129, 123, 125, 126]. These are all based on gate delay models that are compatible with geometric programming; see =-=[77, 121, 135, 120, 1]-=- for more on such models. Work on interconnect sizing (also addressed in this paper) includes [4, 39, 41, 40, 42, 43, 32, 30, 54, 79, 89, 90, 124]; simultaneous gate and wire sizing is considered in [... |

70 | Dual-Threshold Voltage Techniques for Low-power Digital Circuits
- Kao, Chandrakasan
(Show Context)
Citation Context ...s to low power CMOS design have been proposed in the literature, including design with multiple supply and threshold voltages [26, 71, 81, 82, 86, 97, 131, 134, 148], multiple threshold CMOS (MTCMOS) =-=[6, 7, 23, 75]-=-, variable threshold CMOS (VTCMOS) via adaptive body biasing [66, 74, 138, 145], dynamic threshold CMOS (DTCMOS) [9], joint device sizing and Vdd/Vth assignment [10, 11, 27, 65, 80, 76, 92, 104, 108],... |

63 | Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOS
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Citation Context ...ic threshold CMOS (DTCMOS) [9], joint device sizing and Vdd/Vth assignment [10, 11, 27, 65, 80, 76, 92, 104, 108], dynamic frequency scaling [94], supply voltage scaling [12], and transistor stacking =-=[70, 102]-=-. In this section, we show how GP-based approaches can be combined with the techniques above. In particular, the adaptive body biasing, DTCMOS, supply voltage scaling, and dynamic threshold voltage co... |

60 | Speed and power scaling of srams
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Citation Context ... a few, passes over the circuit. Logical effort has been widely used for gate sizing; see, e.g., [48, 117]. Specific applications include adder design [128] and fast low power decoder design for RAMs =-=[13]-=-. (The circuit sizing problems formulated in these papers can all be cast as GPs.) As the authors of [135] make clear, the main point of the logical effort method is not to solve the delay minimizatio... |

50 | Simultaneous driver and wire sizing for performance and power optimization
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(Show Context)
Citation Context ... all based on gate delay models that are compatible with geometric programming; see [77, 121, 135, 120, 1] for more on such models. Work on interconnect sizing (also addressed in this paper) includes =-=[4, 39, 41, 40, 42, 43, 32, 30, 54, 79, 89, 90, 124]-=-; simultaneous gate and wire sizing is considered in [29, 69]. In some of these papers, the authors develop custom methods for solving the resulting GPs, instead of using general purpose interior-poin... |

50 |
Timing models for MOS circuits
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(Show Context)
Citation Context ... the capacitances. This modified version of the Elmore delay can be used when the initial voltages are not all equal to one. There is a large literature on Elmore delay and related topics; see, e.g., =-=[5, 78, 73, 55, 53, 64]-=-. Rubenstein et al. [120] published the simple closed-form formula described above for computing the mean of the impulse response of RC interconnect trees. A general technique to compute higher-order ... |

47 |
Statistical timing analysis using bounds and selective enumeration
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(Show Context)
Citation Context ...erformance specifications. The formulation (12) is a stochastic optimization problem. The statistical analysis and design of digital circuits is an area of growing interest and importance; see, e.g., =-=[2, 14, 21, 72, 106, 107]-=-. This is still an active research area, and no consensus has emerged as to what the best statistical models are. In the following sections, we base our development on some simple models that have bee... |

47 | A 175mV Multiply-Accumulate Unit using an Adaptive Supply Voltage and
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(Show Context)
Citation Context ...long with device sizes, design variables to be optimized. Supply and threshold voltage optimization, in the context of low power CMOS circuit design, is an area of active current research; see, e.g., =-=[7, 24, 28, 74, 108, 134]-=-. Many 34sapproaches to low power CMOS design have been proposed in the literature, including design with multiple supply and threshold voltages [26, 71, 81, 82, 86, 97, 131, 134, 148], multiple thres... |

46 | Closed Form Solution to Simultaneous Buffer Insertion/Sizing and Wire Sizing
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(Show Context)
Citation Context ...ustom methods for solving the resulting GPs, instead of using general purpose interior-point methods (see, e.g., [36, 68, 149]). For some simple problems, analytic solutions are available (see, e.g., =-=[34, 54]-=-). Other problems in digital circuit design where GP plays a role include buffering and wire sizing [3, 34, 35], sizing and placement [33, 93], yield maximization [83, 110], parasitic reduction [115],... |

42 |
Design and optimization of dual threshold circuits for low voltage low power applications
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Citation Context ... posynomial). The fractional error (D − � D)/D of this approximation is smaller than 1% over the range of interest, Vdd ≥ 2Vth, 1.3 ≤ α ≤ 2. Many other gate delay models used in the literature (e.g., =-=[31, 142]-=-) are compatible with GP. For instance, a gate delay model [142] of the form � � Vdd β D = γ + (Vdd − Vth) α 1.5Vdd − Vth g(x, C L , τ in ), where β, γ are process dependent parameters, can also be ex... |

41 |
Dynamic Sleep Transistor and Body Bias for Active Leakage Power Control of Microprocessors
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Citation Context ...design with multiple supply and threshold voltages [26, 71, 81, 82, 86, 97, 131, 134, 148], multiple threshold CMOS (MTCMOS) [6, 7, 23, 75], variable threshold CMOS (VTCMOS) via adaptive body biasing =-=[66, 74, 138, 145]-=-, dynamic threshold CMOS (DTCMOS) [9], joint device sizing and Vdd/Vth assignment [10, 11, 27, 65, 80, 76, 92, 104, 108], dynamic frequency scaling [94], supply voltage scaling [12], and transistor st... |

40 | The Elmore Delay as Bound for RC Trees with Generalized Input Signals
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Citation Context ... the capacitances. This modified version of the Elmore delay can be used when the initial voltages are not all equal to one. There is a large literature on Elmore delay and related topics; see, e.g., =-=[5, 78, 73, 55, 53, 64]-=-. Rubenstein et al. [120] published the simple closed-form formula described above for computing the mean of the impulse response of RC interconnect trees. A general technique to compute higher-order ... |

38 |
Optimization-based transistor sizing
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Citation Context ...ound to be a GP. Since then many digital circuit design problems have been formulated as GPs or related problems. Work on gate and device sizing (the main topics of this paper) can be found in, e.g., =-=[36, 109, 38, 77, 98, 111, 111, 129, 123, 125, 126]-=-. These are all based on gate delay models that are compatible with geometric programming; see [77, 121, 135, 120, 1] for more on such models. Work on interconnect sizing (also addressed in this paper... |

37 | An analytical delay model for RLC interconnects
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(Show Context)
Citation Context ... the capacitances. This modified version of the Elmore delay can be used when the initial voltages are not all equal to one. There is a large literature on Elmore delay and related topics; see, e.g., =-=[5, 78, 73, 55, 53, 64]-=-. Rubenstein et al. [120] published the simple closed-form formula described above for computing the mean of the impulse response of RC interconnect trees. A general technique to compute higher-order ... |

34 | Simple Accurate Expressions for Planar Spiral Inductances
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(Show Context)
Citation Context ...16]. Geometric programming has also been used for the design of non-digital circuits, e.g., analog circuits [45, 59, 60, 96, 140], mixed-signal circuits [37, 57, 58] and RF (radio frequency) circuits =-=[61, 101, 100, 144]-=-. Geometric programming has also been used in floorplanning, for both analog and digital circuits [99]. Our focus will not be on any particular sizing problem, and certainly not on the particular resu... |

33 | Dynamic threshold voltage MOSFET (DTMOS) for ultra low voltage VLSI
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Citation Context ...26, 71, 81, 82, 86, 97, 131, 134, 148], multiple threshold CMOS (MTCMOS) [6, 7, 23, 75], variable threshold CMOS (VTCMOS) via adaptive body biasing [66, 74, 138, 145], dynamic threshold CMOS (DTCMOS) =-=[9]-=-, joint device sizing and Vdd/Vth assignment [10, 11, 27, 65, 80, 76, 92, 104, 108], dynamic frequency scaling [94], supply voltage scaling [12], and transistor stacking [70, 102]. In this section, we... |

33 |
Dual-Threshold Voltage Assignment with Transistor Sizing for Low Power CMOS Circuits
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(Show Context)
Citation Context ...long with device sizes, design variables to be optimized. Supply and threshold voltage optimization, in the context of low power CMOS circuit design, is an area of active current research; see, e.g., =-=[7, 24, 28, 74, 108, 134]-=-. Many 34sapproaches to low power CMOS design have been proposed in the literature, including design with multiple supply and threshold voltages [26, 71, 81, 82, 86, 97, 131, 134, 148], multiple thres... |

32 | On Gate Level Power Optimization Using DualSupply Voltages
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(Show Context)
Citation Context ...long with device sizes, design variables to be optimized. Supply and threshold voltage optimization, in the context of low power CMOS circuit design, is an area of active current research; see, e.g., =-=[7, 24, 28, 74, 108, 134]-=-. Many 34sapproaches to low power CMOS design have been proposed in the literature, including design with multiple supply and threshold voltages [26, 71, 81, 82, 86, 97, 131, 134, 148], multiple thres... |

31 |
Statistical timing analysis of combinational logic circuits,” Very Large Scale Integration (VLSI) Systems
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(Show Context)
Citation Context ...erformance specifications. The formulation (12) is a stochastic optimization problem. The statistical analysis and design of digital circuits is an area of growing interest and importance; see, e.g., =-=[2, 14, 21, 72, 106, 107]-=-. This is still an active research area, and no consensus has emerged as to what the best statistical models are. In the following sections, we base our development on some simple models that have bee... |

31 | Methods for true energy-performance optimization
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(Show Context)
Citation Context ... current research; see, e.g., [7, 24, 28, 74, 108, 134]. Many 34sapproaches to low power CMOS design have been proposed in the literature, including design with multiple supply and threshold voltages =-=[26, 71, 81, 82, 86, 97, 131, 134, 148]-=-, multiple threshold CMOS (MTCMOS) [6, 7, 23, 75], variable threshold CMOS (VTCMOS) via adaptive body biasing [66, 74, 138, 145], dynamic threshold CMOS (DTCMOS) [9], joint device sizing and Vdd/Vth a... |

30 | Equivalent Elmore delay for RLC trees
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(Show Context)
Citation Context ...d wire sizing is considered in [29, 69]. In some of these papers, the authors develop custom methods for solving the resulting GPs, instead of using general purpose interior-point methods (see, e.g., =-=[36, 68, 149]-=-). For some simple problems, analytic solutions are available (see, e.g., [34, 54]). Other problems in digital circuit design where GP plays a role include buffering and wire sizing [3, 34, 35], sizin... |

30 | Minimizing total power by simultaneous Vdd/Vth Assignment
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(Show Context)
Citation Context |

29 | GPCAD: A tool for CMOS op-amp synthesis
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(Show Context)
Citation Context ...ximization [83, 110], parasitic reduction [115], clock tree design [141, 127], and routing [16]. Geometric programming has also been used for the design of non-digital circuits, e.g., analog circuits =-=[45, 59, 60, 96, 140]-=-, mixed-signal circuits [37, 57, 58] and RF (radio frequency) circuits [61, 101, 100, 144]. Geometric programming has also been used in floorplanning, for both analog and digital circuits [99]. Our fo... |

29 |
Duet: An Accurate Leakage Estimation and Optimization Tool for Dual-Vth Circuits
- Sirichotiyakul, Edwards, et al.
- 2002
(Show Context)
Citation Context ... current research; see, e.g., [7, 24, 28, 74, 108, 134]. Many 34sapproaches to low power CMOS design have been proposed in the literature, including design with multiple supply and threshold voltages =-=[26, 71, 81, 82, 86, 97, 131, 134, 148]-=-, multiple threshold CMOS (MTCMOS) [6, 7, 23, 75], variable threshold CMOS (VTCMOS) via adaptive body biasing [66, 74, 138, 145], dynamic threshold CMOS (DTCMOS) [9], joint device sizing and Vdd/Vth a... |

27 |
Optimal Wiresizing Under Elmore Delay Model
- Cong, Leung
- 1995
(Show Context)
Citation Context ... all based on gate delay models that are compatible with geometric programming; see [77, 121, 135, 120, 1] for more on such models. Work on interconnect sizing (also addressed in this paper) includes =-=[4, 39, 41, 40, 42, 43, 32, 30, 54, 79, 89, 90, 124]-=-; simultaneous gate and wire sizing is considered in [29, 69]. In some of these papers, the authors develop custom methods for solving the resulting GPs, instead of using general purpose interior-poin... |

27 |
Gate Oxide Leakage Current Analysis and Reduction for VLSI Circuits
- Lee, Blaauw, et al.
(Show Context)
Citation Context ... formulated and solved as GGPs. Multiple threshold voltage design can be carried out via multiple doping concentrations, multiple channel lengths, multiple oxide thicknesses, and various combinations =-=[88, 132]-=-. (Recently, a multiple oxide thickness and dual supply voltage device approach has become popular in e-DRAMs to achieve high performance and low leakage power [137].) As with joint 39sdevice sizing a... |

26 | Minimization of Dynamic and Static Power Through Joint Assignment of Threshold Voltages and Sizing
- Nguyen
(Show Context)
Citation Context ... threshold CMOS (MTCMOS) [6, 7, 23, 75], variable threshold CMOS (VTCMOS) via adaptive body biasing [66, 74, 138, 145], dynamic threshold CMOS (DTCMOS) [9], joint device sizing and Vdd/Vth assignment =-=[10, 11, 27, 65, 80, 76, 92, 104, 108]-=-, dynamic frequency scaling [94], supply voltage scaling [12], and transistor stacking [70, 102]. In this section, we show how GP-based approaches can be combined with the techniques above. In particu... |

26 | Conscious CAD Tools and Methodologies: a Perspective - Singh - 1995 |

25 |
A New Class of Convex Functions for Delay Modeling and their Application to the Transistor Sizing Problem
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(Show Context)
Citation Context ...roull, Sutherland, and Harris, is almost entirely devoted to the sizing problem. Sizing of digital circuits is a well researched field, with hundreds of papers on the topic; 2ssee, e.g., the articles =-=[52, 109, 32, 83, 77, 124, 126]-=- and the references therein. 1.2 Sizing optimization via geometric programming In this paper we focus on a particular approach, in which the sizing problem is modeled (at least approximately) as a geo... |