## Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation

Citations: | 1 - 0 self |

### BibTeX

@MISC{Lu_totalpower,

author = {Yuanlin Lu and Vishwani D. Agrawal},

title = {Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation},

year = {}

}

### OpenURL

### Abstract

Compared to subthreshold leakage, dynamic power is normally much less sensitive to the process variation due to its approximately linear relation to the process parameters. However, the average dynamic power of a circuit optimized by deterministic glitch elimination (using hazard filtering and path balancing) increases because glitches randomly start reappearing under the influence of process variation. Combining existing techniques, we propose a new statistical mixed integer linear programming (MILP) formulation, which combines glitch elimination and dual-threshold design to statistically minimize the total power in a glitch-free circuit under process variation. 1.

### Citations

43 | An efficient algorithm for statistical minimization of total power under timing yield constraints. DAC
- Mani, Devgan, et al.
- 2005
(Show Context)
Citation Context ... for leakage optimization by dualVth assignment has been proposed [2] using two pruning criteria that stochastically identify pareto-optimal solutions and prune the sub-optimal ones. Another approach =-=[1]-=- solves the statistical leakage minimization problem by a theoretically rigorous formulation for dualVth assignment and gate sizing. Glitches are unnecessary signal transitions that account for 20%-70... |

18 | Minimum dynamic power CMOS circuit design by a reduced constraint set linear program
- Raja, Agrawal, et al.
- 2003
(Show Context)
Citation Context ..., Auburn University, Auburn, AL 36849, USA. 1063-9667/08 $25.00 © 2008 IEEE DOI 10.1109/VLSI.2008.29 21st International Conference on VLSI Design 531 527 hazard filtering [5, 8-12] and path balancing =-=[6, 8, 11]-=-, referred to in this paper as glitch elimination. Compared to leakage power, dynamic power is normally much less sensitive to the process variation because of its approximately linear dependency on t... |

14 | Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method
- Agrawal, Bushnell, et al.
- 1999
(Show Context)
Citation Context ..., Auburn University, Auburn, AL 36849, USA. 1063-9667/08 $25.00 © 2008 IEEE DOI 10.1109/VLSI.2008.29 21st International Conference on VLSI Design 531 527 hazard filtering [5, 8-12] and path balancing =-=[6, 8, 11]-=-, referred to in this paper as glitch elimination. Compared to leakage power, dynamic power is normally much less sensitive to the process variation because of its approximately linear dependency on t... |

13 |
Low Power Design by Hazard Filtering
- Agrawal
- 1997
(Show Context)
Citation Context ...ical and Computer Engineering, Auburn University, Auburn, AL 36849, USA. 1063-9667/08 $25.00 © 2008 IEEE DOI 10.1109/VLSI.2008.29 21st International Conference on VLSI Design 531 527 hazard filtering =-=[5, 8-12]-=- and path balancing [6, 8, 11], referred to in this paper as glitch elimination. Compared to leakage power, dynamic power is normally much less sensitive to the process variation because of its approx... |

12 | Using Gate Sizing to Reduce Glitch Power - Berkelaar, Jacobs - 1996 |

10 | Leakage and dynamic glitch power minimization using integer linear programming for assignment and path balancing - Lu, Agrawal - 2005 |

9 |
New path balancing algorithm for glitch power reduction
- Kim, Kim, et al.
- 2001
(Show Context)
Citation Context ..., Auburn University, Auburn, AL 36849, USA. 1063-9667/08 $25.00 © 2008 IEEE DOI 10.1109/VLSI.2008.29 21st International Conference on VLSI Design 531 527 hazard filtering [5, 8-12] and path balancing =-=[6, 8, 11]-=-, referred to in this paper as glitch elimination. Compared to leakage power, dynamic power is normally much less sensitive to the process variation because of its approximately linear dependency on t... |

8 | Process-Variation-Resistant Dynamic Power Optimization for VLSI Circuits - Hu - 2006 |

7 | Input-specific dynamic power optimization for VLSI circuits - Hu, Agrawal - 2006 |

6 |
Statistical Leakage and Timing Optimization for Submicron Process Variation
- Lu, Agrawal
(Show Context)
Citation Context ...inserted to balance path delays. Statistical delay and leakage models are further adopted to reduce the total power in glitch-free circuits considering process variation. 2. Background Lu and Agrawal =-=[17]-=- propose a statistical MILP formulation to minimize the impact of process variation on the subthreshold leakage. In this section, we extend that discussion to study the impact of process variation on ... |

5 |
Probabilistic dual-vth optimization under variability
- Davoodi, Srivastava
(Show Context)
Citation Context ... circuit performance by dual-Vth assignment. Leakage current and delay are treated as random variables. A dynamic programming approach for leakage optimization by dualVth assignment has been proposed =-=[2]-=- using two pruning criteria that stochastically identify pareto-optimal solutions and prune the sub-optimal ones. Another approach [1] solves the statistical leakage minimization problem by a theoreti... |

4 | Statistical Optimization of Leakage Power Considering - Srivastava, Sylvester, et al. |

4 |
CMOS Leakage and Glitch Power Minimization for Power-Performance Tradeoff
- Lu, Agrawal
- 2006
(Show Context)
Citation Context ...ts either increase or decrease by the same percentage when global process variation is considered, and Tmax (critical path delay that affects the circuit performance) is assumed to change accordingly =-=[15]-=-. The impact of process variation on glitch power is different and more complicated. Glitches are generated if the glitch filtering condition (2) [6] is not satisfied for cell i. Since inertial gate d... |

2 | Nossek, "Transistor Sizing for Switching Activity Reduction in Digital Circuits - Schimpfle, Wroblewski, et al. - 1999 |

2 | Nossek, "Automated Transistor Sizing Algorithm for Minimizing Spurious Switching Activities in CMOS Circuits - Wroblewski, Schimpfle, et al. |

1 | Variable Input Delay - Raja, Agrawal, et al. |