## Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation

### BibTeX

@MISC{Lu_totalpower,

author = {Yuanlin Lu and Vishwani D. Agrawal},

title = {Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation},

year = {}

}

### OpenURL

### Abstract

Compared to subthreshold leakage, dynamic power is normally much less sensitive to the process variation due to its approximately linear relation to the process parameters. However, the average dynamic power of a circuit optimized by deterministic glitch elimination (using hazard filtering and path balancing) increases because glitches randomly start reappearing under the influence of process variation. Combining existing techniques, we propose a new statistical mixed integer linear programming (MILP) formulation, which combines glitch elimination and dual-threshold design to statistically minimize the total power in a glitch-free circuit under process variation. 1.

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Citation Context ... for leakage optimization by dualVth assignment has been proposed [2] using two pruning criteria that stochastically identify pareto-optimal solutions and prune the sub-optimal ones. Another approach =-=[1]-=- solves the statistical leakage minimization problem by a theoretically rigorous formulation for dualVth assignment and gate sizing. Glitches are unnecessary signal transitions that account for 20%-70... |

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Citation Context ..., Auburn University, Auburn, AL 36849, USA. 1063-9667/08 $25.00 © 2008 IEEE DOI 10.1109/VLSI.2008.29 21st International Conference on VLSI Design 531 527 hazard filtering [5, 8-12] and path balancing =-=[6, 8, 11]-=-, referred to in this paper as glitch elimination. Compared to leakage power, dynamic power is normally much less sensitive to the process variation because of its approximately linear dependency on t... |

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Citation Context ...ical and Computer Engineering, Auburn University, Auburn, AL 36849, USA. 1063-9667/08 $25.00 © 2008 IEEE DOI 10.1109/VLSI.2008.29 21st International Conference on VLSI Design 531 527 hazard filtering =-=[5, 8-12]-=- and path balancing [6, 8, 11], referred to in this paper as glitch elimination. Compared to leakage power, dynamic power is normally much less sensitive to the process variation because of its approx... |

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Citation Context ..., Auburn University, Auburn, AL 36849, USA. 1063-9667/08 $25.00 © 2008 IEEE DOI 10.1109/VLSI.2008.29 21st International Conference on VLSI Design 531 527 hazard filtering [5, 8-12] and path balancing =-=[6, 8, 11]-=-, referred to in this paper as glitch elimination. Compared to leakage power, dynamic power is normally much less sensitive to the process variation because of its approximately linear dependency on t... |

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Citation Context ..., Auburn University, Auburn, AL 36849, USA. 1063-9667/08 $25.00 © 2008 IEEE DOI 10.1109/VLSI.2008.29 21st International Conference on VLSI Design 531 527 hazard filtering [5, 8-12] and path balancing =-=[6, 8, 11]-=-, referred to in this paper as glitch elimination. Compared to leakage power, dynamic power is normally much less sensitive to the process variation because of its approximately linear dependency on t... |

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Citation Context ...inserted to balance path delays. Statistical delay and leakage models are further adopted to reduce the total power in glitch-free circuits considering process variation. 2. Background Lu and Agrawal =-=[17]-=- propose a statistical MILP formulation to minimize the impact of process variation on the subthreshold leakage. In this section, we extend that discussion to study the impact of process variation on ... |

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Citation Context ... circuit performance by dual-Vth assignment. Leakage current and delay are treated as random variables. A dynamic programming approach for leakage optimization by dualVth assignment has been proposed =-=[2]-=- using two pruning criteria that stochastically identify pareto-optimal solutions and prune the sub-optimal ones. Another approach [1] solves the statistical leakage minimization problem by a theoreti... |

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Citation Context ...ts either increase or decrease by the same percentage when global process variation is considered, and Tmax (critical path delay that affects the circuit performance) is assumed to change accordingly =-=[15]-=-. The impact of process variation on glitch power is different and more complicated. Glitches are generated if the glitch filtering condition (2) [6] is not satisfied for cell i. Since inertial gate d... |

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