## Variable Input Delay CMOS Logic for Low Power Design (2005)

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Venue: | Auburn University |

Citations: | 4 - 0 self |

### BibTeX

@INPROCEEDINGS{Raja05variableinput,

author = {Tezaswi Raja and Vishwani D. Agrawal and Michael L. Bushnell},

title = {Variable Input Delay CMOS Logic for Low Power Design},

booktitle = {Auburn University},

year = {2005},

pages = {596--604}

}

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### Abstract

Modern digital circuits consist of logic gates implemented in the complementary metal oxide semiconductor (CMOS) technology. The time taken for a logic gate output to change after one or more inputs have changed is called the delay of the gate. A conventional CMOS gate is designed to have the same input to output delay irrespective of which input caused the output to change. We propose a new gate design that has different delays along various input to output paths within the gate. This is accomplished by inserting selectively sized “permanently on ” series transistors at the inputs of the logic gate. We demonstrate the use of the variable input delay CMOS gates for a totally glitch-free minimum dynamic power implementation of a digital circuit. Applying a previously described linear programming method to the c7552 benchmark circuit, we obtained a power saving of 58 % over an unoptimized design. This power consumption was 18% lower than that for an alternative low power design using conventional CMOS gates. All circuits had the same overall delay. Since the overall delay was not allowed to increase, the glitch elimination with conventional gates required insertion of delay buffers on non-critical paths. The use of the variable input delay gates drastically reduced the required number of delay buffers. 1

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Citation Context ...ve mentioned techniques. Following remark has been inserted in the revised paper at the end of Section 1 (see page 4 of revised paper): “Other power reduction techniques such as dual-Vdd and dual-Vth =-=[21, 36]-=- can be used in addition to the present technique to improve the design quality and that does not reduce the power saving from this technique. Recent papers [19,20] combine the glitch elimination and ... |

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Citation Context ...ors. Results show an average energy savings of 58% 4 Conclusion We have proposed a new variable input delay gate design, which has different delays along different input-output paths through the gate =-=[20]-=-. This new design has applications to low power design of digital CMOS circuits. Using the new gate design significant Proc. 18th International Conference on VLSI Design, Jan. 3-7, 2005, pp. 596-604. ... |

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Citation Context ...e in analog layout design but can be used for this purpose. The advantage of using these cells is the continuous controllability of resistance rather than the discrete control provided by transistors =-=[34, 35]-=-. 2.1 Design Issues There are several design issues regarding the variable input delay gate design. The delay along a path can be changed by changing the series resistance. Rs is a function of the len... |

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Citation Context ...e in analog layout design but can be used for this purpose. The advantage of using these cells is the continuous controllability of resistance rather than the discrete control provided by transistors =-=[34, 35]-=-. 2.1 Design Issues There are several design issues regarding the variable input delay gate design. The delay along a path can be changed by changing the series resistance. Rs is a function of the len... |

2 | Variable Input Delay CMOS Logic Design for Low Dynamic Power Circuits - Raja, Agrawal, et al. - 2005 |