Reconfigurable hardware implementation of mesh routing in number field sieve factorization”, Special Purpose Hardware for Attacking Cryptographic Systems (2005)
| Venue: | in the Number Field Sieve Factorization,” Proc. Field Programmable Technology Conf. (FPT’04 |
| Citations: | 2 - 2 self |
BibTeX
@INPROCEEDINGS{Bajracharya05reconfigurablehardware,
author = {Sashisu Bajracharya and Deapesh Misra and Kris Gaj and Tarek El-ghazawi},
title = {Reconfigurable hardware implementation of mesh routing in number field sieve factorization”, Special Purpose Hardware for Attacking Cryptographic Systems},
booktitle = {in the Number Field Sieve Factorization,” Proc. Field Programmable Technology Conf. (FPT’04},
year = {2005}
}
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Abstract
Factorization of large numbers has been a constant source of interest in cryptanalysis. The fastest known algorithm for factoring large numbers is the Number Field Sieve (NFS). The two most time consuming phases of NFS are Sieving and Matrix Step. In this paper, we propose an efficient way of implementing the Matrix step in reconfigurable hardware. Our solution is based on the Mesh-Routing method proposed by Lenstra et al. We determine the practical size of a partial mesh that can fit in one FPGA device, Xilinx Virtex II XC2V8000. We further extrapolate the computation time for the case of a square systolic array of FPGAs for 512-bit and 1024-bit numbers' factorization. We demonstrate that for practical sizes of numbers used in cryptography, 1024 bits, the Matrix Step of factorization can be performed using 1024 Virtex II FPGAs in about 27 days. 1.
