Mixed Swing Techniques for Low Energy/Operation Datapath Circuits

Mixed Swing Techniques for Low Energy/Operation Datapath Circuits (1997)

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[128.2.129.29]

by Ram Kumar Krishnamurthy

Citations:

5 - 0 self

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@TECHREPORT{Krishnamurthy97mixedswing,
    author = {Ram Kumar Krishnamurthy},
    title = {Mixed Swing Techniques for Low Energy/Operation Datapath Circuits},
    institution = {},
    year = {1997}
}

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Abstract

The portable communications industry’s vision of integrating a complete multimedia complex on a single die, coupled with the desktop computing industry’s vision of inte-grating multimedia functionality into general-purpose microprocessors has trans-formed lowering the power dissipation of digital signal processing (DSP) datapath circuits into an increasingly important challenge in current and future fabrication pro-cesses. Fully-static CMOS logic accompanied with supply voltage scaling has enjoyed widespread usage in lowering datapath power dissipation over the last decade. How-ever, fundamental limitations preclude device threshold voltage scaling under the con-stant drain-source field scaling paradigm in future deep-submicron processes, imposing limitations on voltage scaling. This has motivated a strong necessity for exploring new methodologies to lower the power dissipation of next-generation high-speed datapath circuits. This thesis investigates Mixed Swing techniques for reducing the power dissipa-tion of static CMOS datapath operators while retaining their high performance, or

Citations

291	A neutral netlist of 10 combinational benchmark circuits and a target translator - Brglez, Fujiwara - 1985
216	Alpha-power law MOSFET model and its applications to CMOS inverter and other formulas - Sakurai, Newton - 1990
166	A Suggestion for a Fast Multiplier - Wallace - 1964
147	TILOS: A Posynomial Programming Approach to Transistor Sizing - Fishburn, Dunlop - 1985
95	Packaging for VLSI - Bakoglu, Circuits - 1990
81	An exact solution to the transistor sizing problem for cmos circuits using convex optimization - Sapatnekar, Rao, et al. - 1993
71	CMOS circuit speed and buffer optimization - Hedenstierna, Jeppson - 1987
57	Trading Speed for Low Power by Choice of Supply and Threshold Voltages - Liu, Svensson - 1993
49	Noise in deep submicron digital design - Shepard, Narayanan - 1996
43	Power Estimation for High Level Synthesis - Landman, Rabaey
37	Geometric programming: methods, computations and applications - Ecker - 1980
27	CMOS Scaling for High Performance and Low Power – The Next Ten Years - Davari, Dennard, et al. - 1995
27	Power dissipation analysis and optimization of deep submicron CMOS digital circuits - Gu, Elmasry - 1996
27	Sub-1-V Swing Internal Bus Architecture for Future Low-Power ULSI’s - Nakagome - 1993
25	A 200mV Self-Testing Encoder/Decoder using Stanford Ultra-Low-Power CMOS - Burr, Shott - 1994
21	A comparison of CMOS circuit techniques: Differential cascode voltage switch logic versus conventional logic - Chu, Pulfrey - 1987
20	A Self-Terminating LowVoltage Swing CMOS Output Driver - Knight, Krimm - 1988
17	Power Estimation Techniques for Integrated Circuits - NAJM - 1995
16	NORA: A Race-free Dynamic CMOS Technique for Pipelined Logic Structure - Goncalves, Mari - 1983
15	Testing for Bridging Faults (Shorts - Acken - 1983
14	A signed binary multiplication technique," Quarterly - Booth - 1951
12	Analysis of glitch power dissipation in CMOS IC’s - Favalli, Benini - 1995
10	Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area, and dynamic power dissipation - Hoppe, Neuendorf, et al. - 1990
10	Performance of CMOS Differential Circuits - Ng, Balsara, et al. - 1996
9	Circuit Techniques for CMOS Low-Power High-Performance Multipliers - Khater, Bellaouar, et al. - 1996
9	Low-Power Design Techniques for HighPerformance CMOS - Ko, Balsara, et al. - 1995
9	Exploring the Design Space of Mixed Swing Quadrail for Low-Power Digital Circuits - Krishnamurthy, Carley - 1997
9	A 300MHz CMOS Microprocessor with Multi-Media Technology - Choudhury, Miller - 1997
8	Power-Supply Voltage Impact on Circuit Performance for Half and Lower Submicrometer CMOS LSI - Kakumu, Kinugawa - 1990
8	CMOS current steering logic for low-voltage mixed signal integrated circuits - Ng, Allstot - 1997
7	Computer architecture for digital signal processing - Allen - 1985
6	Static Power driven voltage scaling and delay driven buffer sizing - Krishnamurthy, Lys, et al. - 1996
6	Computer Aided Design for VLSI Circuit Manufacturability - Maly - 1990
6	A gate level simulator for power consumption analysis - Pursley - 1996
5	SO1 CMOS as a Mainstream Low-Power Technology: A Critical Assessmerit - Antoniadis - 1997
5	Supply and Threshold Voltage Optimizations for Low Power Design - Frank, Solomon, et al. - 1997
5	A Swing Restored Pass-Transistor Logic-Based Multiply and Accumulate Circuit for Multimedia Applications - Parameswar, Hara, et al. - 1996
4	et al., "A 1.5ns, 32b CMOS ALU in Double Pass-Transistor Logic - Suzuki - 1993
4	Effects of random MOSFET parameter fluctuations on total power consumption - Tang, De, et al. - 1996
3	A CMOS Wave-pipelined Image Processor for Real-time Morphology - Krishnamurthy, Sridhar - 1995
3	Zipper CMOS - Lee, Szeto - 1986
3	private communication - Corp, Belgium - 2000
2	QuadRail: A Design Methodology for Ultra Low Power Integrated Circuits - Carley - 1994
2	et al., "A low-power design method using multiple supply voltages - Igarashi - 1997
2	A 0.25 µm CMOS 0.9V 100 MHz DSP - Izumikawa - 1997
2	Mixed Swing QuadRail: Exploring Multiple Voltage Swings for Low Energy/Operation - Krishnamurthy, Lys, et al. - 1996
2	Delay Analysis of Series� Connected MOSFET Circuits - Newton� - 1991
2	et al, "A 1-V High-speed MTCMOS Circuit Scheme for Power-down Applications - Shigematsu - 1997
2	LVDCSL: Low voltage differential current switch logic, a robust low power DCSL family - Somasekhar, Roy - 1997
2	et al, "Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits - Su - 1993