## Mixed Swing Techniques for Low Energy/Operation Datapath Circuits (1997)

Citations: | 5 - 0 self |

### BibTeX

@TECHREPORT{Krishnamurthy97mixedswing,

author = {Ram Kumar Krishnamurthy},

title = {Mixed Swing Techniques for Low Energy/Operation Datapath Circuits},

institution = {},

year = {1997}

}

### OpenURL

### Abstract

The portable communications industry’s vision of integrating a complete multimedia complex on a single die, coupled with the desktop computing industry’s vision of inte-grating multimedia functionality into general-purpose microprocessors has trans-formed lowering the power dissipation of digital signal processing (DSP) datapath circuits into an increasingly important challenge in current and future fabrication pro-cesses. Fully-static CMOS logic accompanied with supply voltage scaling has enjoyed widespread usage in lowering datapath power dissipation over the last decade. How-ever, fundamental limitations preclude device threshold voltage scaling under the con-stant drain-source field scaling paradigm in future deep-submicron processes, imposing limitations on voltage scaling. This has motivated a strong necessity for exploring new methodologies to lower the power dissipation of next-generation high-speed datapath circuits. This thesis investigates Mixed Swing techniques for reducing the power dissipa-tion of static CMOS datapath operators while retaining their high performance, or

### Citations

345 |
A Neutral Netlist of 10 Combinational Benchmark Designs and a Special Translator
- Brglez, Fujiwara
- 1985
(Show Context)
Citation Context ... sizing. The effect of optimal voltage scaling and buffer transistor sizing on QuadRail’s power-delay characteristics was first demonstrated on a 17-net ISCAS’85 combinational benchmark circuit (c17) =-=[Brglez85]-=- in the 0.5μm process, achieving up to 2.2X improvement in energy/operation [Krishna97]. Motivated by these results, we examine the effectiveness of these optimization techniques for a 16*16+36-bit Qu... |

297 |
Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas
- Sakurai, Newton
- 1990
(Show Context)
Citation Context ...h between V dd and ground as shown in Figure 2, during which both the NMOS and PMOS devices conduct simultaneously causing the short-circuit current I sc to flow. This short-circuit power is given by =-=[Sakurai90]-=-: P sc 1 1 α ----------i n + 1 n 1 2 (EQ 3) where, n is the velocity saturation index, typically between 1.0-1.5 in submi– -------------- β n 1 -- ( V 2 dd – ( V tn + V tp ) ) + = ⋅ ⋅ ⋅ ⋅ ⋅ t T ⋅ f cl... |

226 |
A suggestion for a fast multiplier
- Wallace
- 1964
(Show Context)
Citation Context ... are added to produce two final 2n-1 bit vectors using Carry Save Adders (CSAs). Partial product reduction can be accomplished using either an array topology [Cavanagh84] or a (Wallace) tree topology =-=[Wallace64]-=-, as illustrated in Figure 9(c). Array topologies have a logic depth of O(n) and a regular structure, enabling easy layout. Wallace trees employ a parallel reduction scheme and have a logic depth of O... |

176 |
Tilos: A posynomial programming approach to transistor-sizing
- Fishburn, Dunlop
- 1985
(Show Context)
Citation Context ...imum of the function is a guaranteed global minimum. Posynomial models for power and delay are widely used for solving transistor sizing and gate sizing optimization problems for static CMOS circuits =-=[Fishburn85]-=-, [Sapatnekar93]. One traditional approach employed in transistor-level optimization problems to model CMOS circuits is by modeling CMOS gates as RC-trees [Bakoglu90]. However, these models can deviat... |

112 |
Packaging for VLSI
- Bakoglu, “Circuits
- 1990
(Show Context)
Citation Context ...y gate such as in ratioed logic families, or, (ii) the requirement of additional input-data-unrelated switching signals to perform the logic gate’s function, such as in dynamic/clocked logic families =-=[Bakoglu90]-=-. Such techniques have traditionally been employed in high-speed digital circuits, where contrary to low-power design objectives, total power, much less extraneous power, is not a design issue. The fu... |

96 | An exact solution to the Transistor Sizing Problem for CMOS Circuits using convex optimization
- Sapatnekar, Rao, et al.
- 1993
(Show Context)
Citation Context ...nction is a guaranteed global minimum. Posynomial models for power and delay are widely used for solving transistor sizing and gate sizing optimization problems for static CMOS circuits [Fishburn85], =-=[Sapatnekar93]-=-. One traditional approach employed in transistor-level optimization problems to model CMOS circuits is by modeling CMOS gates as RC-trees [Bakoglu90]. However, these models can deviate significantly ... |

79 |
CMOS circuit speed and buffer optimization
- Hedenstierna, Jeppson
- 1987
(Show Context)
Citation Context ...ations for QuadRail power and delay. Further, we take into consideration input waveform slope (approximated as a ramp signal), because of its significant contribution to delay and short circuit power =-=[Heden87]-=-. Our models are derived as functions of n, and hence they may be used to explore QuadRail’s design space in various current and future submicron processes. 5.1.1 Analytical Delay Model Defining Δ as ... |

66 | Noise in deep submicron digital design
- Shepard, Narayanan
- 1996
(Show Context)
Citation Context ... Energy/Operation Datapath Circuits 117sMixed Swing Circuits: Low-Voltage Challenges with process scaling has made designing for signal integrity an increasingly formidable research challenge as well =-=[Shepard96]-=-. Both manufacturability and noise immunity worsen with voltage scaling, due to the increased dispersion in circuit operating frequency, power dissipation, and noise margins across worst-case process ... |

65 |
Trading speed for low power by choice of supply and threshold voltages
- Liu, Svensson
- 1993
(Show Context)
Citation Context ...shold voltages and operating voltages to Mixed Swing Techniques for Low Energy/Operation Datapath Circuits 35sBackground: Static CMOS Low-Voltage Design alleviate the speed penalty of voltage scaling =-=[Liu93]-=-, [Burr94], [Gu96], [Frank97]. As shown in Figure 6, scaling threshold voltage and power supply simultaneously offers an exponential increase in static power and a quadratic reduction in dynamic power... |

47 |
Power estimation for high level synthesis
- Landman, Rabaey
- 1993
(Show Context)
Citation Context ...uadratic impact on it [Chandra95]. In addition, datapath operators display high switching activities due to their intrinsically high static transition probabilities and spurious/glitching transitions =-=[Landman93]-=-, [Chandra95], [Favalli95], [Nagamatsu95], [Najm95]. This makes their effective switched capacitance per cycle substantial. These factors, coupled with their high-throughput demands, accounts for the ... |

41 |
Geometric programming: Methods, computations and applications
- Ecker
- 1980
(Show Context)
Citation Context ...de-offs in QuadRail circuits. We propose to model both QuadRail power and delay as posynomial functions of buffer transistor size. A posynomial function P(k) of a positive variable k ∈R is defined as =-=[Ecker80]-=-: m b ij Pk ( ) = ∑a j ⋅ ∏ k i j i = 1 (EQ 7) The coefficients a j must be positive and b ij must be real. Posynomial functions exhibit the distinct property that a local minimum of the function is a ... |

31 |
Power Dissipation Analysis and Optimization of Deep Submicron CMOS Digital Circuits
- Gu, Elmasry
- 1996
(Show Context)
Citation Context ...operating voltages to Mixed Swing Techniques for Low Energy/Operation Datapath Circuits 35sBackground: Static CMOS Low-Voltage Design alleviate the speed penalty of voltage scaling [Liu93], [Burr94], =-=[Gu96]-=-, [Frank97]. As shown in Figure 6, scaling threshold voltage and power supply simultaneously offers an exponential increase in static power and a quadratic reduction in dynamic power; since the latter... |

31 |
Sub-1-V swing internal bus architecture for future low-power ULSI’s
- Nakagome, Itoh, et al.
- 1993
(Show Context)
Citation Context ...ultiple Voltage Techniques Multiple power supply-based techniques were originally developed to lower the power consumption of long off-chip [FutureBus83], [Knight88] and onchip [Bakoglu85], [Shin89], =-=[Nakagome93]-=-, [Sakurai97] buses. The motive behind these techniques is to drive the bus at a reduced voltage swing to lower Mixed Swing Techniques for Low Energy/Operation Datapath Circuits 61sMixed Swing Techniq... |

28 | CMOS scaling for high performance and low power- the next ten years - Davari, Dennard, et al. - 1995 |

26 |
A 200mV Self-Testing Encoder/Decoder using Stanford Ultra-Low-Power CMOS
- Burr, Scott
- 1994
(Show Context)
Citation Context ...tages and operating voltages to Mixed Swing Techniques for Low Energy/Operation Datapath Circuits 35sBackground: Static CMOS Low-Voltage Design alleviate the speed penalty of voltage scaling [Liu93], =-=[Burr94]-=-, [Gu96], [Frank97]. As shown in Figure 6, scaling threshold voltage and power supply simultaneously offers an exponential increase in static power and a quadratic reduction in dynamic power; since th... |

26 |
A comparison of CMOS circuit techniques: Differential cascode voltage switch logic versus conventional logic." Solid-State Circuits
- Chu, Pulfrey
- 1987
(Show Context)
Citation Context ... cost of increased static DC bias currents; this contributes to high static power consumption. These factors have rendered them both power and speed inefficient except for large-fanin gate structures =-=[Chu87]-=-, [Soma97]. 2.5.4 Adiabatic Logic-based techniques Fully-dynamic and quasi-static energy recovery logic approaches have been proposed to lower the power consumption of static CMOS circuits [De96], [Ye... |

20 |
A self-terminating low-voltage swing CMOS output driver
- Knight, Krymm
- 1988
(Show Context)
Citation Context ... processes is demonstrated. 4.1 Background: Multiple Voltage Techniques Multiple power supply-based techniques were originally developed to lower the power consumption of long off-chip [FutureBus83], =-=[Knight88]-=- and onchip [Bakoglu85], [Shin89], [Nakagome93], [Sakurai97] buses. The motive behind these techniques is to drive the bus at a reduced voltage swing to lower Mixed Swing Techniques for Low Energy/Ope... |

18 | n-p-CMOS: A racefree dynamic CMOS technique for pipelined logic structures
- Goncalves, Man
- 1982
(Show Context)
Citation Context ... Design gory, we now review the most interesting approaches, with an emphasis on their applicability in future deep-submicron processes. 2.5.1 Dynamic Logic-based techniques Domino CMOS [Krambeck82], =-=[Goncalves83]-=-, Zipper CMOS [Lee86], and Clocked CMOS [Bakoglu90] approaches have been proposed for improved speed and lower power than static CMOS logic. Unfortunately, dynamic techniques require single- or multi-... |

18 | Power Estimation Techniques for Integrated Circuits
- Najm
- 1995
(Show Context)
Citation Context ...th operators display high switching activities due to their intrinsically high static transition probabilities and spurious/glitching transitions [Landman93], [Chandra95], [Favalli95], [Nagamatsu95], =-=[Najm95]-=-. This makes their effective switched capacitance per cycle substantial. These factors, coupled with their high-throughput demands, accounts for the dynamic power dominance. Short-circuit power also c... |

15 |
Testing for Bridging Faults (Shorts
- Acken
- 1983
(Show Context)
Citation Context ...ssipation contributes to an 36 R.K. KrishnamurthysVoltage Scaling unacceptably high off-state power [Chandra96]. The high leakage currents also prevent the effective usage of I DDQ testing approaches =-=[Acken83]-=-, commonly employed for detecting power-ground short-circuit/bridging faults [Shigematsu95]. These factors have made effective control of the threshold variations and the high leakage power with scali... |

15 | Circuit Techniques for CMOS Low-power High- performance Multipliers - Ahu-Khater, Bellaouar, et al. - 1996 |

14 | A signed binary multiplication technique," Quarterly - Booth - 1951 |

13 |
Optimization of High-Speed CMOS Logic Circuits with Analytical Models for Signal Delay
- Hoppe, Neuendorf, et al.
- 1990
(Show Context)
Citation Context ...l optimization problems to model CMOS circuits is by modeling CMOS gates as RC-trees [Bakoglu90]. However, these models can deviate significantly from SPICE simulations, yielding suboptimal solutions =-=[Hoppe90]-=-. This is primarily due to not considering MOSFET short-channel effects which become significant at submicron feature sizes. On the other hand, developing accurate short-channel analytical models requ... |

13 |
Low-power design techniques for high- performance CMOS adders
- KO, Balsara, et al.
- 1995
(Show Context)
Citation Context ...y product (PDP), i.e., power*delay, and energy-delay product (EDP), i.e., power*(delay) 2 , two commonly employed metrics to compare power-delay trade-offs between circuit methodologies [Horowitz94], =-=[Ko95]-=-. Figure 30 shows the PDP and EDP for the same experimental setup as in Figure 27. Since V logic has orthogonal effects on power and delay, and since both QuadRail power and delay are posynomial funct... |

12 |
Analysis of glitch power dissipation in CMOS ICs
- Favalli, Benini
- 1995
(Show Context)
Citation Context ...ndra95]. In addition, datapath operators display high switching activities due to their intrinsically high static transition probabilities and spurious/glitching transitions [Landman93], [Chandra95], =-=[Favalli95]-=-, [Nagamatsu95], [Najm95]. This makes their effective switched capacitance per cycle substantial. These factors, coupled with their high-throughput demands, accounts for the dynamic power dominance. S... |

11 | Performance of CMOS Differential Circuits - Ng, Balsara, et al. - 1996 |

11 |
J.S.Miller, "A 300MHz CMOS microprocessor with multi-media technology
- Choudhury
- 1997
(Show Context)
Citation Context ...ext-generation general-purpose microprocessors. This is primarily because of the rapidly increasing integration of dedicated FPU-intensive multimedia instructions in modern processors [Ultrasparc95], =-=[Pentium97]-=-. FIGURE 57 Single-supply CMOS vs. QuadRail Power vs. T clk comparisons for 24*24+56-bit MAC. Multiplier Power (mW) 100 3v 10 1 10 3.1X 3,2.1v 2.5,1.6v 2.5v 3.4X 2,1.1v 2v 4.05X off-chip reg. QuadRail... |

10 |
Exploring the Design Space of Mixed Swing QuadRail for Low Power Digital Circuits
- Krishnamurthy, Carley
- 1997
(Show Context)
Citation Context ... Datapath Circuits 71sMixed Swing Techniques cesses, for a given load capacitance and transistor aspect ratios, the buffer stage delay is related to load voltage swing and on-drive voltage as follows =-=[Krishna97]-=-: (EQ 5) where V t is the threshold voltage and n is the velocity saturation index. n indicates the degree of carrier velocity saturation of the transistors, and is close to FIGURE 20 Mixed Swing Quad... |

9 |
Power-supply voltage impact on circuit performance for half and lower submicrometer CMOS
- Kakumu, Kinugawa
- 1990
(Show Context)
Citation Context ...margins across worst-case process and temperature corners at reduced voltages. This makes design for manufacturability and noise immunity all the more important in low-voltage deep-submicron circuits =-=[Kakumu90]-=-, [Yan95], [Strojwas96]. In this chapter, we examine these two low-voltages challenges to study the practicality of mixed swing methodologies. Worst-case analysis is performed on a 16*16+36-bit MAC im... |

8 | Supply and threshold voltage optimization for low power design
- Frank, Solomon, et al.
- 1997
(Show Context)
Citation Context ...g voltages to Mixed Swing Techniques for Low Energy/Operation Datapath Circuits 35sBackground: Static CMOS Low-Voltage Design alleviate the speed penalty of voltage scaling [Liu93], [Burr94], [Gu96], =-=[Frank97]-=-. As shown in Figure 6, scaling threshold voltage and power supply simultaneously offers an exponential increase in static power and a quadratic reduction in dynamic power; since the latter typically ... |

8 |
CMOS current steering logic for low-voltage mixed signal integrated circuits
- Ng, Allstot
- 1997
(Show Context)
Citation Context ... routing both true and complimentary signals, necessitate single- or multi-phase clocks for operation (in some schemes), and display relatively lower noise immunity. Current-steering logic techniques =-=[Ng97]-=- have been developed which exhibit improved noise immunity, but high-speed is achieved at the cost of increased static DC bias currents; this contributes to high static power consumption. These factor... |

7 |
Computer architecture for digital signal processing
- Allen
- 1985
(Show Context)
Citation Context ... circuit delay path and hence determines the operating 18 R.K. KrishnamurthysThesis Focus clock frequency; many DSPs characterize their performance in terms of the number of MACs performed per second =-=[Allen85]-=-, [Lapsley96]. Further, datapath operators display high switching activity due to both inherently high static transition probabilities and considerable amount of spurious transitions due to dynamic ha... |

7 | Static power driven voltage scaling and delay driven buffer sizing
- Krishnamurthy, Lys, et al.
- 1996
(Show Context)
Citation Context ...stribution vs. output bit-position. Delay 2N-1 MSB 70 R.K. Krishnamurthy 0 LSB output bit-positionsThe Mixed Swing QuadRail Methodology loads at the gate outputs at reduced voltage swings [Carley94], =-=[Krishna96a]-=-, [Krishna96b]. The essence of the Mixed Swing QuadRail methodology is that it allows exploitation of the best aspects of both voltage scaling and full swing static CMOS within a single logic gate. Fi... |

6 |
SOI CMOS as a Mainstream Low-Power Technology
- Antoniadis
- 1997
(Show Context)
Citation Context ...ional partial- or fully-depleted SOI devices restricts their applicability in SOI processes. Although non-conventional body-tied SOI devices are being developed to overcome this restriction [Yang95], =-=[Antoniadis97]-=-, [Douseki97], no commercial solutions have been reported to date. 2.4 Multiple Threshold CMOS Approaches Multiple threshold voltage (multiple-well) approaches have been proposed to mitigate the afore... |

6 |
Computer Aided Design for VLSI Circuit Manufacturability
- Maly
(Show Context)
Citation Context ... channel length (ΔL), and channel width (ΔW): this is due to the strong correlation between NMOS and PMOS devices in these parameter variations that precludes them from varying in opposite directions =-=[Maly90]-=-. On the other hand, variations in NMOS and PMOS threshold voltages do not exhibit a strong correlation and hence vary in opposite directions. Figure 35 explains this trend: NMOS and PMOS threshold vo... |

6 |
A swing restored passtransistor logic-based multiply and accumulate circuit for multimedia applications
- Parameswar, Hara, et al.
- 1996
(Show Context)
Citation Context ... concern as clock frequency. 2.5.2 Pass-transistor Logic-based techniques Single-ended and fully-differential pass-transistor and transmission-gate logic techniques [Yano90], [Suzuki93], [Krishna95], =-=[Param96]-=-, [Yano96], have been proposed as high-speed and/or low-power alternatives to the static CMOS methodology. However, since outputs of pass-transistors do not swing rail-torail, these approaches incorpo... |

6 |
A gate level simulator for power consumption analysis
- Pursley
- 1996
(Show Context)
Citation Context ... switching activity within the multiplier using unit-delay-model-based transition counting techniques reveals an activity factor of nearly 1.17, with up to 46% of the total transitions being spurious =-=[Pursley97]-=-. These factors make the effective switched capacitance per cycle substantial; the reduced voltage swing across this capacitance accounts for our energy/operation savings. In addition, HSPICE simulati... |

6 |
private communication
- Osborg, Corp, et al.
(Show Context)
Citation Context ...ii) signal crosstalk, and (iii) substrate coupling [Bakoglu90]. On the basis of experimental measurements on the 16*16+36-bit MAC fabricated in the 0.5μm process and commercial low-voltage noise data =-=[Stanisic97]-=-, [Nicol97], worst-case noise within the static CMOS and QuadRail MACs are computed, shown in Table 3. Figure 43 shows the leftover worst-case noise margins after allocating these noise values superim... |

5 |
Zipper CMOS
- Lee, Szeto
- 1986
(Show Context)
Citation Context ... the most interesting approaches, with an emphasis on their applicability in future deep-submicron processes. 2.5.1 Dynamic Logic-based techniques Domino CMOS [Krambeck82], [Goncalves83], Zipper CMOS =-=[Lee86]-=-, and Clocked CMOS [Bakoglu90] approaches have been proposed for improved speed and lower power than static CMOS logic. Unfortunately, dynamic techniques require single- or multi-phase clock signals t... |

4 |
et al., "A 1.5ns, 32b CMOS ALU in Double Pass-Transistor Logic
- Suzuki
- 1993
(Show Context)
Citation Context ...re power is not as much a concern as clock frequency. 2.5.2 Pass-transistor Logic-based techniques Single-ended and fully-differential pass-transistor and transmission-gate logic techniques [Yano90], =-=[Suzuki93]-=-, [Krishna95], [Param96], [Yano96], have been proposed as high-speed and/or low-power alternatives to the static CMOS methodology. However, since outputs of pass-transistors do not swing rail-torail, ... |

4 |
Effects of random MOSFET parameter fluctuations on total power consumption
- Tang, De, et al.
- 1996
(Show Context)
Citation Context ...uctuations. The variations have been projected to increase at least linearly with decreasing feature sizes, becoming comparable to the threshold voltages themselves [Yan95], [Eisele95], [Strojwas96], =-=[Tang96]-=-. The threshold variations also cause increased delay and power dispersion [Sun94], [Davari96], [Frank97], with operating voltage scaling, degrading low-voltage manufacturability [Strojwas96]. As an e... |

3 |
QuadRail: A Design Methodology for Ultra Low Power Integrated Circuits
- Carley, Lys
- 1994
(Show Context)
Citation Context ...ree delay distribution vs. output bit-position. Delay 2N-1 MSB 70 R.K. Krishnamurthy 0 LSB output bit-positionsThe Mixed Swing QuadRail Methodology loads at the gate outputs at reduced voltage swings =-=[Carley94]-=-, [Krishna96a], [Krishna96b]. The essence of the Mixed Swing QuadRail methodology is that it allows exploitation of the best aspects of both voltage scaling and full swing static CMOS within a single ... |

3 |
A CMOS Wave-pipelined Image Processor for Real-time Morphology
- Krishnamurthy, Sridhar
- 1995
(Show Context)
Citation Context ...not as much a concern as clock frequency. 2.5.2 Pass-transistor Logic-based techniques Single-ended and fully-differential pass-transistor and transmission-gate logic techniques [Yano90], [Suzuki93], =-=[Krishna95]-=-, [Param96], [Yano96], have been proposed as high-speed and/or low-power alternatives to the static CMOS methodology. However, since outputs of pass-transistors do not swing rail-torail, these approac... |

3 |
Limitation of CMOS Supply Voltage Scaling by MOSFET Threshold Voltage Variation
- Sun, Tsui
- 1994
(Show Context)
Citation Context ...ecreasing feature sizes, becoming comparable to the threshold voltages themselves [Yan95], [Eisele95], [Strojwas96], [Tang96]. The threshold variations also cause increased delay and power dispersion =-=[Sun94]-=-, [Davari96], [Frank97], with operating voltage scaling, degrading low-voltage manufacturability [Strojwas96]. As an example, measurements on a commercial 3V, 0.4μm bulkCMOS process with nominal thres... |

2 |
et al., "A low-power design method using multiple supply voltages
- Igarashi
- 1997
(Show Context)
Citation Context ...of clustered voltage scaling to the same example MAC circuit. The critical and non-critical path gates are isolated into separate routing channels in the layout and tied to independent power supplies =-=[Igarashi97]-=-. The critical path gates operate at a regular, high voltage (V dd ) to meet the target throughput of F clk . The non-critical path gates operate at a lower voltage V dd /z exploiting the delay slack ... |

2 |
A 0.25 µm CMOS 0.9V 100 MHz DSP
- Izumikawa
- 1997
(Show Context)
Citation Context ... trend for three commercial CMOS DSPs and general-purpose RISC processors targeted for DSP applications: the datapath power component ranges from 39% [Wailee97a], [Wailee97b] up to 50% [Nagamatsu95], =-=[Izumikawa97]-=- of their respective total power. Therefore, there exists a strong necessity to focus attention on lowering the power consumption of DSP datapath circuits in general, and MAC circuits in particular. T... |

2 |
Mixed Swing QuadRail: Exploring Multiple Voltage Swings for Low Energy/Operation
- Krishnamurthy, Lys, et al.
- 1996
(Show Context)
Citation Context ... output bit-position. Delay 2N-1 MSB 70 R.K. Krishnamurthy 0 LSB output bit-positionsThe Mixed Swing QuadRail Methodology loads at the gate outputs at reduced voltage swings [Carley94], [Krishna96a], =-=[Krishna96b]-=-. The essence of the Mixed Swing QuadRail methodology is that it allows exploitation of the best aspects of both voltage scaling and full swing static CMOS within a single logic gate. Figure 20 shows ... |

2 |
Design Trade-Offs
- Nagendra, Irwin
- 1996
(Show Context)
Citation Context ...tage is introduced between the multiplier and final adder [Lu93], [Nagamatsu95], Mixed Swing Techniques for Low Energy/Operation Datapath Circuits 51sDSP MAC Circuits: Power-Delay Trade-offs [Jou95], =-=[Nagendra96]-=-, [Murakami96], [Izumikawa97]. An added bonus due to the inserted pipeline stage is that it offers considerable reduction in spurious transitions, which depend quadratically on logic gate depth [Chand... |

2 | Delay Analysis of Series� Connected MOSFET Circuits - Newton� - 1991 |

2 |
et al, "A 1-V High-speed MTCMOS Circuit Scheme for Power-down Applications
- Shigematsu
- 1997
(Show Context)
Citation Context ...f-state power [Chandra96]. The high leakage currents also prevent the effective usage of I DDQ testing approaches [Acken83], commonly employed for detecting power-ground short-circuit/bridging faults =-=[Shigematsu95]-=-. These factors have made effective control of the threshold variations and the high leakage power with scaling threshold voltages prime challenges towards the applicability of technology-driven volta... |