Demodulator for Space Communications
BibTeX
@MISC{Yuce_demodulatorfor,
author = {Mehmet R. Yuce and Wentai Liu and John Damiano and Bhaskar Bharat and Paul D. Franzon and Numan S. Dogan},
title = {Demodulator for Space Communications},
year = {}
}
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Abstract
Abstract—A low power PSK demodulator integrated circuit (IC) has been implemented using Silicon On Insulator (SOI) CMOS technology for deep space and satellite applications. The demodulator employs double differential detection to increase its robustness to the Doppler shift caused by the movement of the space vehicle and sampling technique with 1-bit A/D converter at the front to reduce the complexity and power dissipation. In particular, digital decimation is used after sampling to achieve a low power implementation of multirate transmission. Operating at UHF frequency (435 MHz), the receiver system supports a wide range of data rates (0.1-100 Kbps). From test results, the power consumption of the demodulator circuit including the 1-bit A/D converter is below 1 mW for data rates up to 100 Kbps. Index Terms—Phase-Shift Keying (PSK), differential detection, space communications, symbol timing circuit, multirate, sampling. D I.
