## A Fitting Approach to Generate Symbolic Expressions for Linear and Nonlinear Analog Circuit Performance Characteristics (2002)

Venue: | In Proceedings Design Automation and Test in Europe Conference |

Citations: | 4 - 1 self |

### BibTeX

@INPROCEEDINGS{Daems02afitting,

author = {Walter Daems and Georges Gielen and Willy Sansen},

title = {A Fitting Approach to Generate Symbolic Expressions for Linear and Nonlinear Analog Circuit Performance Characteristics},

booktitle = {In Proceedings Design Automation and Test in Europe Conference},

year = {2002},

pages = {268--273}

}

### OpenURL

### Abstract

This paper presents a novel method to automatically generate symbolic expressions for both linear and nonlinear circuit characteristics using a template-based fitting of numerical, simulated data. The aim of the method is to generate convex, interpretable expressions. The posynomiality of the generated expressions enables the use of efficient geometric programming techniques when using these expressions for circuit sizing and optimization. Attention is paid to estimating the relative `goodness-of-fit' of the generated expressions. Experimental results illustrate the capabilities of the approach.

### Citations

306 |
Statistics for experimenters: an introduction to design, data analysis, and model building, p. 571–583
- Box, Hunter, et al.
- 1978
(Show Context)
Citation Context ... experiments The theory of Design Of Experiments (DOE) provides a mathematical basis to select an optimal sample set that allows an uncorrelated estimation of the fit parameters, given a fit template =-=[30]-=-. The number of sampling schemes described in literature is vast: starting from full- and fractional factorial design, over Placket-Burman and Taguchi schemes, to Latin hypercube and even random desig... |

119 |
Orthogonal Arrays: Theory and Applications
- Hedayat, Sloane, et al.
- 1999
(Show Context)
Citation Context ...Burman and Taguchi schemes, to Latin hypercube and even random design. A sampling scheme that allows an uncorrelated estimation of the coefficients of (11) are level-3 orthogonal arrays of strength 3 =-=[31]. Th-=-is scheme places the sampling points on the edges of a fitting hypercube of size ∆X around a center point X ∗ . Usually the center point is provided as well. This sampling scheme has been chosen, ... |

73 |
Sansen, Distortion Analysis of Analog Integrated Circuits, 1st ed
- Wambacq, M
- 1998
(Show Context)
Citation Context ...echniques generate network functions like � p i=0 aisi H(s) = �p . (1) j=0 bjsj More recently, some promising extensions towards pole-zero analysis [18], [19], [20], [21], [22] and nonlinear analy=-=sis [23]-=-, [24] also emerged. The traditional approach used in symbolic analysis for linear (or linearized) analog circuits has been depicted on the left-hand side of Fig. 1. The approach starts with an AC exp... |

63 | Optimal design of a CMOS opamp via geometric programming
- Hershenson, Boyd, et al.
- 2001
(Show Context)
Citation Context ...ted to be used over a larger part of the design space during circuit design. 6. The technique generates posynomial expressions [25]. This allows to formulate the sizing problem as a geometric program =-=[26]-=-, [27]. The paper is organized as follows. Section 2 will provide some theoretical background. In section 3, we will discuss our approach in detail. The proposed approach has been implemented in a sof... |

50 |
Geometric Programming - Theory and Applications
- Duffin, Peterson, et al.
- 1967
(Show Context)
Citation Context ...esigner is interested is fully covered. Therefore the expressions are suited to be used over a larger part of the design space during circuit design. 6. The technique generates posynomial expressions =-=[25]-=-. This allows to formulate the sizing problem as a geometric program [26], [27]. The paper is organized as follows. Section 2 will provide some theoretical background. In section 3, we will discuss ou... |

38 |
An infeasible interior-point algorithm for solving primal and dual geometric programs
- Kortanek, Xu, et al.
- 1996
(Show Context)
Citation Context ...en that the transformed problem is a convex optimization problem. Because of this, it has only one global optimum. In addition, this optimum can be found very efficiently using interior point methods =-=[28]-=-, even for large problems. Notice that strictly speaking posynomial expressions are not convex: the above mentioned transformation makes them convex. However, in view of that property, we conveniently... |

29 |
A Symbolic Simulator for Analog Integrated Circuits
- Gielen, Sansen
- 1989
(Show Context)
Citation Context ...ore, it is an important research topic in the analog electronic design area. While symbolic analysis research started much earlier, the first research boom is located in the 1980s [2], [3], [4], [5], =-=[6]-=-, [7] mainly due to the wider availability of computing equipment. Soon it became obvious that the size of the circuits that could be analyzed was severely restricted by the exponential relationship b... |

19 |
Flowgraph analysis of large electronic networks
- Starzyk, Konczykowska
- 1986
(Show Context)
Citation Context ...subtask. Therefore, it is an important research topic in the analog electronic design area. While symbolic analysis research started much earlier, the first research boom is located in the 1980s [2], =-=[3]-=-, [4], [5], [6], [7] mainly due to the wider availability of computing equipment. Soon it became obvious that the size of the circuits that could be analyzed was severely restricted by the exponential... |

17 |
Cmos op-amp sizing using a geometric programming formulation
- Mandal, Visvanathan
- 2001
(Show Context)
Citation Context ... be used over a larger part of the design space during circuit design. 6. The technique generates posynomial expressions [25]. This allows to formulate the sizing problem as a geometric program [26], =-=[27]-=-. The paper is organized as follows. Section 2 will provide some theoretical background. In section 3, we will discuss our approach in detail. The proposed approach has been implemented in a software ... |

16 |
Efficient symbolic computation of approximated small-signal characteristics
- Wambacq, Fernandez, et al.
- 1994
(Show Context)
Citation Context ...size of the circuit. Therefore, the research focus restricted itself more and more towards enabling the analysis of larger linear circuits by employing all sorts of approximation techniques [8], [9], =-=[10]-=-, [11], [12], [13], [14]. The developed approximation techniques are based on exploiting the numerical differences in order of magnitude of the small-signal parameters. In most techniques reported in ... |

16 | Symbolic analysis of large analog circuits with determinant decision diagrams
- Shi, Tan
- 1997
(Show Context)
Citation Context ...f the circuit. Therefore, the research focus restricted itself more and more towards enabling the analysis of larger linear circuits by employing all sorts of approximation techniques [8], [9], [10], =-=[11]-=-, [12], [13], [14]. The developed approximation techniques are based on exploiting the numerical differences in order of magnitude of the small-signal parameters. In most techniques reported in litera... |

14 |
Synthesis Tools for Mixed-Signal ICs
- Carley, Gielen, et al.
- 1996
(Show Context)
Citation Context ...og and mixed-signal circuits. Automation of this process is currently an important research target in the electronic design automation business. The sizing process can be decomposed into two subtasks =-=[1]: • one -=-“investigates” the circuit’s behavior (knowledge acquisition), and • one adjusts the design parameters according to the obtained knowledge (knowledge use) Symbolic analysis tries to automate t... |

13 |
Approximate symbolic analysis of large analog integrated circuits
- Yu, Sechen
- 1994
(Show Context)
Citation Context ... the size of the circuit. Therefore, the research focus restricted itself more and more towards enabling the analysis of larger linear circuits by employing all sorts of approximation techniques [8], =-=[9]-=-, [10], [11], [12], [13], [14]. The developed approximation techniques are based on exploiting the numerical differences in order of magnitude of the small-signal parameters. In most techniques report... |

11 |
Simulation-based automatic generation of signomial and posynomial performance models for analog integrated circuit sizing
- Daems, Gielen, et al.
- 2001
(Show Context)
Citation Context ... 4-bit word (a3a2a1a0). The algorithm can be found in Fig. 4. This algorithm keeps the terms of (11) that have positive coefficients and replaces the negative terms by appropriate approximations (see =-=[29]-=-). The number of terms of the estimated templates is at most 1/2n 2 +5/2n +1. In order to keep the template as sparse as possible, the estimation correlation between the coefficients of (11) should be... |

10 |
A symbolic analysis tool for analog circuit design automation
- Seda, Degrauwe, et al.
- 1988
(Show Context)
Citation Context ...herefore, it is an important research topic in the analog electronic design area. While symbolic analysis research started much earlier, the first research boom is located in the 1980s [2], [3], [4], =-=[5]-=-, [6], [7] mainly due to the wider availability of computing equipment. Soon it became obvious that the size of the circuits that could be analyzed was severely restricted by the exponential relations... |

10 |
Equation-Based Symbolic Approximation by Matrix Reduction with Quantitative Error Prediction
- Sommer, Hennig, et al.
- 1993
(Show Context)
Citation Context ...s and the size of the circuit. Therefore, the research focus restricted itself more and more towards enabling the analysis of larger linear circuits by employing all sorts of approximation techniques =-=[8]-=-, [9], [10], [11], [12], [13], [14]. The developed approximation techniques are based on exploiting the numerical differences in order of magnitude of the small-signal parameters. In most techniques r... |

8 | Efficient DDD-based symbolic analysis of large linear analog circuits
- Verhaegen, Gielen
- 2001
(Show Context)
Citation Context ...refore, the research focus restricted itself more and more towards enabling the analysis of larger linear circuits by employing all sorts of approximation techniques [8], [9], [10], [11], [12], [13], =-=[14]-=-. The developed approximation techniques are based on exploiting the numerical differences in order of magnitude of the small-signal parameters. In most techniques reported in literature these differe... |

5 |
K.S.: Symbolic analysis of large-scale networks using a hierarchical signal flowgraph approach
- Hassoun, McCarville
- 1993
(Show Context)
Citation Context ...ned by numerically analyzing the circuit in a single design point. Another line of research investigated hierarchical techniques, i.e. splitting the symbolic analysis task up in several smaller tasks =-=[15]-=-, [16], [17]. Linear hierarchical techniques typically generate a sequence of expressions relating a network function with the small-signal parameters involved and the Laplace variable s. Flat techniq... |

4 | Circuit complexity reduction for symbolic analysis of analog integrated circuits
- Daems, Gielen, et al.
- 1999
(Show Context)
Citation Context ...t. Therefore, the research focus restricted itself more and more towards enabling the analysis of larger linear circuits by employing all sorts of approximation techniques [8], [9], [10], [11], [12], =-=[13]-=-, [14]. The developed approximation techniques are based on exploiting the numerical differences in order of magnitude of the small-signal parameters. In most techniques reported in literature these d... |

4 |
An efficient dc root solving algoritm with guaranteed convergence for analog integrated cmos circuits
- Leyn, Gielen, et al.
- 1998
(Show Context)
Citation Context ...osynomial formulation). Note that transistor currents and voltages are chosen as variables, rather than transistor widths, since we use an operating-point driven formulation for analog circuit sizing =-=[32]. i x i nominal ��-=-�x i,1 ∆x i,2 ∆x i,3 x i,ref 1 v GS,M1 -0.9V ± 0.2V ± 0.1V ±40mV -4.0V 2 v GS,M2 0.8V ± 0.2V ± 0.1V ±40mV 4.0V 3 v DS,M2 0.5V ± 0.2V ± 0.1V ±40mV 4.0V 4 v GS,M3 2.5V ± 0.2V ± 0.1V ±40m... |

3 |
Symbolic Calculation of Poles and Zeros
- Dröge, Horneber
- 1996
(Show Context)
Citation Context ...rameters involved and the Laplace variable s. Flat techniques generate network functions like � p i=0 aisi H(s) = �p . (1) j=0 bjsj More recently, some promising extensions towards pole-zero analy=-=sis [18]-=-, [19], [20], [21], [22] and nonlinear analysis [23], [24] also emerged. The traditional approach used in symbolic analysis for linear (or linearized) analog circuits has been depicted on the left-han... |

3 |
Symbolic Distortion Analysis of Analog Integrated Circuits
- Verhaegen, Gielen
- 2001
(Show Context)
Citation Context ...ues generate network functions like � p i=0 aisi H(s) = �p . (1) j=0 bjsj More recently, some promising extensions towards pole-zero analysis [18], [19], [20], [21], [22] and nonlinear analysis [2=-=3], [24]-=- also emerged. The traditional approach used in symbolic analysis for linear (or linearized) analog circuits has been depicted on the left-hand side of Fig. 1. The approach starts with an AC expansion... |

2 |
SAPEC: A personal computer program for the symbolic analysis of electric circuits
- Liberatore, Manetti
- 1988
(Show Context)
Citation Context ...sk. Therefore, it is an important research topic in the analog electronic design area. While symbolic analysis research started much earlier, the first research boom is located in the 1980s [2], [3], =-=[4]-=-, [5], [6], [7] mainly due to the wider availability of computing equipment. Soon it became obvious that the size of the circuits that could be analyzed was severely restricted by the exponential rela... |

2 |
Symbolic analysis of large-scale networks by circuit reduction to a two-port
- Pierzchała, Rodanski
- 1996
(Show Context)
Citation Context ... numerically analyzing the circuit in a single design point. Another line of research investigated hierarchical techniques, i.e. splitting the symbolic analysis task up in several smaller tasks [15], =-=[16]-=-, [17]. Linear hierarchical techniques typically generate a sequence of expressions relating a network function with the small-signal parameters involved and the Laplace variable s. Flat techniques ge... |

2 |
Accurate extraction of simplified symbolic pole/zero expressions for large analog ICs
- Hsu, Sechen
- 1995
(Show Context)
Citation Context ...olved and the Laplace variable s. Flat techniques generate network functions like � p i=0 aisi H(s) = �p . (1) j=0 bjsj More recently, some promising extensions towards pole-zero analysis [18], [1=-=9], [20]-=-, [21], [22] and nonlinear analysis [23], [24] also emerged. The traditional approach used in symbolic analysis for linear (or linearized) analog circuits has been depicted on the left-hand side of Fi... |

1 |
Symbolic circuit analysis
- Singhal, Vlach
- 1981
(Show Context)
Citation Context ...irst subtask. Therefore, it is an important research topic in the analog electronic design area. While symbolic analysis research started much earlier, the first research boom is located in the 1980s =-=[2]-=-, [3], [4], [5], [6], [7] mainly due to the wider availability of computing equipment. Soon it became obvious that the size of the circuits that could be analyzed was severely restricted by the expone... |

1 |
Interactive AC modeling and characterization of analog circuits via symbolic analysis
- Fernández-Fernandéz, Rodríguez-Vázquez
- 1991
(Show Context)
Citation Context ...it is an important research topic in the analog electronic design area. While symbolic analysis research started much earlier, the first research boom is located in the 1980s [2], [3], [4], [5], [6], =-=[7]-=- mainly due to the wider availability of computing equipment. Soon it became obvious that the size of the circuits that could be analyzed was severely restricted by the exponential relationship betwee... |

1 |
A simplification before and during generation methodology for symbolic large-circuit analysis
- Guerra, Rodríguez-García, et al.
- 1998
(Show Context)
Citation Context ...circuit. Therefore, the research focus restricted itself more and more towards enabling the analysis of larger linear circuits by employing all sorts of approximation techniques [8], [9], [10], [11], =-=[12]-=-, [13], [14]. The developed approximation techniques are based on exploiting the numerical differences in order of magnitude of the small-signal parameters. In most techniques reported in literature t... |

1 |
True hierarchical symbolic analysis of large-scale analog integrated circuits
- Guerra, Rodríguez-García, et al.
- 1998
(Show Context)
Citation Context ...ically analyzing the circuit in a single design point. Another line of research investigated hierarchical techniques, i.e. splitting the symbolic analysis task up in several smaller tasks [15], [16], =-=[17]-=-. Linear hierarchical techniques typically generate a sequence of expressions relating a network function with the small-signal parameters involved and the Laplace variable s. Flat techniques generate... |

1 |
Symbolic pole/zero calculation using SANTAFE
- Nebel, Kleine, et al.
- 1995
(Show Context)
Citation Context ...rs involved and the Laplace variable s. Flat techniques generate network functions like � p i=0 aisi H(s) = �p . (1) j=0 bjsj More recently, some promising extensions towards pole-zero analysis [1=-=8], [19]-=-, [20], [21], [22] and nonlinear analysis [23], [24] also emerged. The traditional approach used in symbolic analysis for linear (or linearized) analog circuits has been depicted on the left-hand side... |

1 |
A new approach to symbolic pole computation
- Constantinescu, Nitescu
- 1995
(Show Context)
Citation Context ...and the Laplace variable s. Flat techniques generate network functions like � p i=0 aisi H(s) = �p . (1) j=0 bjsj More recently, some promising extensions towards pole-zero analysis [18], [19], [2=-=0], [21]-=-, [22] and nonlinear analysis [23], [24] also emerged. The traditional approach used in symbolic analysis for linear (or linearized) analog circuits has been depicted on the left-hand side of Fig. 1. ... |

1 |
A symbolic pole/zero extraction methodoly based on analysis of circuit time-constants
- Rodríguez-García, Guerra, et al.
- 1999
(Show Context)
Citation Context ...e Laplace variable s. Flat techniques generate network functions like � p i=0 aisi H(s) = �p . (1) j=0 bjsj More recently, some promising extensions towards pole-zero analysis [18], [19], [20], [2=-=1], [22]-=- and nonlinear analysis [23], [24] also emerged. The traditional approach used in symbolic analysis for linear (or linearized) analog circuits has been depicted on the left-hand side of Fig. 1. The ap... |