## A design methodology for highly-integrated low-power receivers for wireless communications (2001)

Citations: | 10 - 0 self |

### BibTeX

@TECHREPORT{Yee01adesign,

author = {Dennis Gee-wai Yee},

title = {A design methodology for highly-integrated low-power receivers for wireless communications},

institution = {},

year = {2001}

}

### OpenURL

### Abstract

### Citations

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Citation Context ...mate given by (5.51) is ⎡ 1 ⎤ 3 2 E⎢max(| I |, | Q |) + min(| I |, | Q |) = σ N 2 ⎥ . (5.65) ⎣ ⎦ 2 π The gain-control algorithm can be implemented using an adaptive least mean squares (LMS) algorithm =-=[56]-=-. The equivalent combiner for a feedback AGC loop based on (5.49) for amplitude estimation is illustrated in Fig. 5.15. The error signal e(k)isgivenby e I Q 2 2 ( k) = d( k) − g( k) x ( k) + x ( k) . ... |

1039 |
Digital Communications
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Citation Context ...sponding signal waveforms for transmission. In a phase-shift keying (PSK) signaling scheme, the data is modulated on the phase of the carrier and the corresponding signal waveforms are represented as =-=[16]-=- s m ⎡ 2π ⎤ ( t) = g( t) cos ⎢ 2π f ct + ( m −1) , m = 1, 2, , M, M ⎥ K ⎣ ⎦ ⎡2π ⎤ ⎡2π ⎤ = g( t) cos ⎢ ( m −1) cos( 2π f ct) g( t) sin ( m 1) sin( 2π f ct) M ⎥ − ⎢ − M ⎥ ⎣ ⎦ ⎣ ⎦ 26 0 ≤ t ≤ T (3.1) wher... |

1023 | Multiuser Detection
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Citation Context ... alternative. In order to increase system performance, receivers are beginning to incorporate more advanced algorithms for timing synchronization [19] and data detection, such as multiuser techniques =-=[52]-=-. While the complexity of these algorithms along with the decreasing supply voltages of CMOS processes result in very challenging analog implementations, these algorithms are actually very well suited... |

404 |
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Citation Context ...unce. In this prototype, the amount of coupling is reduced by implementing the digital portions of the PLL using either source-coupled logic (SCL) or differential cascode voltage switch logic (DCVSL) =-=[79]-=-. Fig. 6.34 illustrates inverter implementations based on these two V in V out Vin V out (a) (b) (c) Figure 6.34: Inverter implementations. (a) Static CMOS. (b) SCL. (c) DCVSL. 182 V in Voutslogic sty... |

305 |
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Citation Context ...circuits are used to implement the baseband amplifiers and filters, device mismatches give rise to dc offsets. For the differential CMOS amplifier illustrated in Fig. 2.9, the input offset voltage is =-=[10]-=- ( V ⎡ ⎤ GS −Vt ) ⎛ − ∆RL ⎞ ⎛ ∆( W / L) ⎞ V = ∆ + ⎢ ⎜ ⎟ OS Vt − ⎜ ⎟⎥ . (2.5) 2 ⎣⎝ RL ⎠ ⎝ ( W / L) ⎠⎦ The dc offset in this case is related to the mismatch in the transistor threshold voltage, the mism... |

270 | Channel assignment schemes for cellular mobile telecommunication systems: a comprehensive survey
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Citation Context ...by restricting transmission distances within each cell to less than 5 m with an aggregate transmit power of 0 dBm at each base station. For hexagonal cells, the cellular reuse factor is restricted to =-=[37]-=- 87s2 2 N = i + ij + j = 3, 4, 7, 9, 12, K (5.7) where i and j are integers. In the case of K = 31, there are six unique 5-bit MLSR sequences [16]. Consequently, a cellular reuse pattern with N = 4 (F... |

263 |
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Citation Context ...ely, of the i th receiver stage. Finally, before concluding this section, it is worthwhile to clarify the distinction between single-sideband (SSB) noise figure and double-sideband (DSB) noise figure =-=[25]-=-. Fig. 4.2 depicts an RF input signal which is corrupted by AWGN. The power and bandwidth of the RF signal are Psig and W, respectively, while the PSD of the AWGN is N / 2 ,and consequently, the input... |

263 |
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Citation Context ...max(|I|,|Q|)+ 2 min(|I|,|Q|) 2 + Q 2 0 0 1 2 3 t (× 2π/∆ω) 4 5 6 Figure 5.14: Amplitude estimates with frequency offset ∆ ω . Q 2 2 E [ I + Q ] = E[ V ] (5.61) 2 2 = I Q is a Rayleigh random variable =-=[55]-=- with mean and variance given The expected value of the estimate given by (5.50) is π E[ V ] = σ N (5.62) 2 ⎛ π ⎞ 2 VAR[ V ] = ⎜2 − ⎟⎠ σ N . (5.63) ⎝ 2 ∞ 2 x − 2 σ 1 2 2 E[| I | + | Q |] = 2 ∫| x | e ... |

201 |
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Citation Context ... from microwave designs using coaxial cables, where the 50-Ω interface resistance is a compromise between the 30-Ω resistance for maximum power handling and the 77-Ω resistance for minimum loss [25], =-=[59]-=-. Integrated-circuit implementations have already abandoned this antiquated requirement, and more recently, the 50-Ω requirement at the interface between external and on-chip components, e.g., between... |

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Citation Context ...frequency synthesizer.sbandwidth of 3 MHz. 6.3.1 Voltage-Controlled Oscillator The phase noise performance of an oscillator at an offset frequency ∆ω from the center frequency ω 0 can be described by =-=[76]-=- 2 ⎪ ⎧ 2FkT ⎡ ⎛ ω ⎞ ⎤⎛ ∆ω ⎞⎪ ⎫ 3 0 1/ f L ( ∆ω) = 10log⎨ ⎢1 + ⎜ ⎟ ⎥⎜1 + ⎟ ⎜ ⎟⎬ (6.131) ⎪⎩ Psig ⎢ ⎥⎝ ∆ ⎣ ⎝ 2Q∆ω ⎠ ω ⎦ ⎠⎪⎭ where F is an excess noise factor, Psig is the output power of the oscillator, ... |

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Citation Context ...te noise models have been proposed for short-channel MOS devices. Two proposed mechanisms resulting in the observed excess thermal noise include high-field effects [65] and induced gate current noise =-=[64]-=-, [65]. MOS Noise Model including High-Field Effects. The first modification to the traditional MOS noise model is an increased drain current noise resulting from high-field effects in short-channel d... |

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Citation Context ...ject problem. Moreover, all of the remaining analog components can be integrated onto a single chip using a single technology such as silicon CMOS, with the exception of the antenna and the RF filter =-=[7]-=-–[9]. However, two practical considerations have limited the use of the direct-conversion architecture: dc offsets and flicker noise. 2.3.1 DC Offsets LNA 0˚ LO (fc) 90˚ Implementations based on the d... |

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Citation Context ...defined in Fig. D.1. The first test structure is a planar spiral inductor implemented using only the top layer of metal, while the second test structure includes a patterned polysilicon ground shield =-=[109]-=-. This ground shield prevents the inductor electric field from penetrating the silicon substrate, which degrades the quality factor of the inductor, while patterning the shield prevents current flow w... |

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Citation Context ...ovides a good compromise between maximally flat gain and linear phase response. Translation of the baseband I and Q signals to the 2-GHz carrier frequency is based on a direct-conversion architecture =-=[39]-=-. The frequency translation is performed using two mixers and an LO fixed at the carrier frequency and operating in quadrature. At the outputs of the two mixers, the I and Q signals are combined befor... |

73 |
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Citation Context ...ons may be achieved for higher-order filters by implementing a second-order transfer function using additional active gain elements, such as the Tow-Thomas biquad illustrated in Fig. 6.40 [20], [83], =-=[84]-=-. The voltage transfer function is given by V V s r r 1 2 + R C 1 1 R R C C out 1 2 4 1 2 = − . (6.135) 2 1 r2 1 in 189 s + r 1 R R C C The key building block for this biquad is the active RC integrat... |

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Citation Context ...s are implemented using unsalicided n+-poly and poly/n-well structures, respectively. The poly/n-well structure operating in 192 50/0.35sC inversion depletion accumulation as illustrated in Fig. 6.45 =-=[90]-=- offers a large capacitive density of about 6fF/µm 2 when biased above the flat-band voltage, VFB, of about 90 mV. The circuit schematic of the high-pass filter is illustrated in Fig. 6.46. The resist... |

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Citation Context ...ion in (5.68) requires the calculation of x Q 2 2 I ( k) + x ( k) , which may be achieved by dividing y(k) inFig.5.15byg(k). This division operation may be eliminated by using the sign-data algorithm =-=[57]-=- instead of the stochastic gradient descent method described above. Adaptation using the sign-data algorithm results in the following update equation: Since (5.74) becomes g I Q 2 2 ( k + 1) = g( k) +... |

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Citation Context ...is limited to about four for processes which rely on low-resisitivity silicon substrates (Appendix D), the equivalent quality factor of ring oscillators is even less with values ranging from 1 to 1.5 =-=[77]-=-. Nevertheless, for applications with relaxed phase noise requirements, the ring-oscillator VCO has two major advantages. First, the area of the ring-oscillator VCO is much less than that of the LC-tu... |

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Citation Context ... flicker noise performance is not well controlled, which is the case in many CMOS processes, circuit techniques such as autozeroing and chopper stabilization can be used to suppress the flicker noise =-=[48]-=-. The autozero technique is typically implemented using a two-phase clock. During the first phase, the circuit with flicker noise is disconnected from the signal path and its flicker noise is sampled ... |

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Citation Context ...tenna as well as DC offsets resulting from LO self-mixing. 6.4.2 Active Mixers A popular active mixer is the double-balanced current-commutating mixer (Fig. 6.36) based on the Gilbert cell multiplier =-=[81]-=-. Unlike passive mixers, active mixers actually provide conversion gain, which relaxes the noise and gain requirements in the subsequent baseband circuits. However, active mixers contribute both therm... |

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Citation Context ...m silicon substrate with a 10-Ω-cm epitaxial layer. A total of seven different inductor structures were designed in ASITIC, a tool which provides rapid analysis, design, and optimization of inductors =-=[107]-=-, [108]. The geometries of the seven inductors are summarized in Table D.1 and the parameters D, W, S, andNare defined in Fig. D.1. The first test structure is a planar spiral inductor implemented usi... |

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Citation Context ...LNA is so critical, an accurate transistor noise model is essential. In particular, the measured thermal noise in short-channel MOS devices is greater than the amount predicted by long-channel theory =-=[61]-=-–[63]. This section begins with a review of the long-channel MOS noise model followed by a discussion of some recently proposed noise models for short-channel MOS devices. Long-Channel MOS Noise Model... |

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Citation Context ...(a) Concept. (b) Implementation. in I out Q out f c LO (f LO1)sRF Input (fc) - A D RF Filter LNA LO1 (fc−fIF) the basis for the image-reject receiver architecture, also called the Weaver architecture =-=[11]-=-, illustrated in Fig. 2.13. Suppose that the signal appearing at the antenna is s desired image ( t) = s ( t) + s ( t) (2.9) where sdesired(t) is the desired signal and simage(t) is the undesired imag... |

38 | Introduction to RF simulation and its application
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Citation Context ...sebandequivalent models for the analog RF building blocks, such as amplifiers, mixers, and oscillators. The method is similar to envelop simulation techniques used in some RF circuit-level simulators =-=[27]-=-. The baseband-equivalent models for the various RF building blocks are based on the following expression which can be used to represent any real signal along the RF signal path: N ∑ n= 1 s( t) = s ( ... |

36 | A single-chip 900MHz CMOS receiver front-end with a high performance low-IF topology - Crols - 1995 |

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Citation Context ...as with any pipeline architecture, is latency. Several low-power ADCs have been implemented based on the pipeline architecture with capacitive scaling, including a 10-bit, 20-MS/s ADC consuming 35 mW =-=[93]-=- and a 10-bit, 40-MS/s ADC consuming 28 mW [94],[95]. The former was implemented in a 1.2-µm process and the latter was implemented in a 0.6-µm process. Although the pipeline architecture is a promisi... |

32 | Rohde,”Microwave Circuit Design Using Linear and Nonlinear Techniques - Vendelin, Pavio, et al. - 1990 |

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Citation Context ...e of the receiver is determined, the noise budget must be partitioned between the various receiver building blocks. For cascaded receiver stages, the total noise factor is given by the Friis equation =-=[24]-=-: F tot F2 −1 FN −1 = F1 + + K + (4.7) N G1 G where Fi and Gi are the noise factor and power gain, respectively, of the i th receiver stage. Finally, before concluding this section, it is worthwhile t... |

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Citation Context ...4 = 200/0.25 L 2 s Vin − Figure 6.18: Inductively-degenerated differential LNA.sG s ' same current consumption, the differential LNA matched to the lowest source conductance has the best noise figure =-=[68]-=-. Unfortunately, the impact of the source conductance on the noise figure was not fully appreciated at the time, and the LNA used in this receiver prototype was designed to match a balanced resistance... |

28 |
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Citation Context ...Figure 6.23: Summary of on-chip spiral inductors. Each of the LNA input bond pads consists of the top three layers of metal, all shorted together, while a fourth lower layer of metal acts as a shield =-=[72]-=-. However, rather than connecting the shield to ground, the shield instead is connected to the source terminal of the input transistor so that the pad capacitance appears in parallel with the gate-sou... |

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Citation Context ...l MOS devices. Recently, more accurate noise models have been proposed for short-channel MOS devices. Two proposed mechanisms resulting in the observed excess thermal noise include high-field effects =-=[65]-=- and induced gate current noise [64], [65]. MOS Noise Model including High-Field Effects. The first modification to the traditional MOS noise model is an increased drain current noise resulting from h... |

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Citation Context ....40: Tow-Thomas biquad. V in V bias (a) (b) (c) Figure 6.41: Integrators. (a) RC. (b) MOSFET-C. (c) Transconductance-C. C Vout r 1 Vin r 2 Gm C Vout VoutsV in φ 2 φ 1 MOSFET-C integrator (Fig. 6.41b) =-=[85]-=- and the transconductance-C integrator (Fig. 6.41c) [86], [87]. In the former case, the resistance R is implemented using an MOS transistor operating in the linear region, and the resistance can be ad... |

23 |
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Citation Context ... each of the input transistors is partitioned into ten blocks of ten fingers of 5 µm × 0.25 µm devices. Fingering the devices helps to reduce the resistance associated with the polysilicon gate [64], =-=[69]-=-. Keeping this resistance small is critical since the noise associated with this resistance appears directly at the input of the LNA. In addition, substrate contacts are placed generously around and b... |

20 | High-frequency CMOS continuous-time filters, " lEEE
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Citation Context ....41: Integrators. (a) RC. (b) MOSFET-C. (c) Transconductance-C. C Vout r 1 Vin r 2 Gm C Vout VoutsV in φ 2 φ 1 MOSFET-C integrator (Fig. 6.41b) [85] and the transconductance-C integrator (Fig. 6.41c) =-=[86]-=-, [87]. In the former case, the resistance R is implemented using an MOS transistor operating in the linear region, and the resistance can be adjusted through the transistor gate bias voltage, Vbias, ... |

19 |
CMOS Wireless Transceiver Design
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Citation Context ...m the desired signal. This requirement, however, is not prohibitively restrictive since many communications systems provide for relaxed interferer levels in nearby frequency channels. For example, in =-=[14]-=-, a GSM (Global System Mobile) receiver is implemented based on the low-IF architecture. GSM is a European digital cellular system which uses a narrowband signaling scheme with a single-sided baseband... |

18 |
Discrete simulation of colored noise and stochastic processes and 1/f α power law noise generation
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Citation Context ...z 50 MHz 80.2 dB 78.7 dB Table 4.1: Effect of noise sampling time on simulation accuracy. 1 | H ( f ) | = . (4.55) fsmagnitude Such a filter can be approximated by the discrete-time transfer function =-=[30]-=- The frequency response of H(z)isgivenby 5 4 3 2 1 1 Ω 0 0 0.5 1 1.5 Ω 2 2.5 3 1/2 1 H . (4.56) ( z) = −1 1/ 2 ( 1− z ) jΩ 1 H ( e ) = (4.57) − jΩ 1/ 2 ( 1− e ) and the magnitude of ( ) Ω j H e is plo... |

17 |
Analog Filter Design
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Citation Context ... signal while rejecting the unwanted frequency components. Several types of filters are commonly used to approximate an ideal low-pass filter response, including the Butterworth and Chebyshev filters =-=[20]-=-. The magnitude response of a Butterworth filter is given by 1 H ( jω ) = (3.23) 2N ⎛ ⎞ 2 1 ⎜ ω + ε ⎟ ⎜ ⎟ ⎝ω p ⎠ where N is the filter order, ωp is the passband edge, and ε determines the magnitude va... |

16 |
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Citation Context ...ure Due to its simplicity and potential for high integration, the direct-conversion architecture (Fig. 2.7) is the most promising candidate for implementing the receiver for the proposed system [46], =-=[47]-=-. As discussed in Sections 2.3.1 and 2.3.2, receiver implementations based on the direct-conversion architecture must contend with dc offsets and flicker noise. Although the low-IF architecture has th... |

15 |
Personal communication radio coverage in buildings at 900 MHz and 1700
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Citation Context ...jects in an indoor transmission environment.sA third model, which is the one used in this work, is a combination of the first two models and has demonstrated a better fit to experimental measurements =-=[44]-=-, [45]: Equation (5.17) can be rewritten as where P R GRGT PT = α PR T 92 2 ⎛ λ ⎞ ⎜ ⎟ ⎝ 4π ⎠ 1 . (5.17) n d [ dBm] = P [ dBm] − L [ dB] (5.18) 2 ⎡ 1 ⎛ 4π ⎞ ⎤ n L [ dB] = 10log⎢ ⎜ ⎟ d ⎥ + α [ dB] . (5.... |

15 |
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Citation Context ... needs to generate only a single carrier frequency and can be implemented using a wide-bandwidth PLL. The wide loop bandwidth of the PLL suppresses the close-in phase noise of the ring-oscillator VCO =-=[78]-=-, thus improving the overall phase noise performance of the frequency synthesizer. 6.3.2 Other Design Considerations A deadzone-free phase-frequency detector (PFD) is used to increase the pull-in rang... |

14 |
MOSFET thermal noise modeling for analog integrated circuits
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Citation Context ...s so critical, an accurate transistor noise model is essential. In particular, the measured thermal noise in short-channel MOS devices is greater than the amount predicted by long-channel theory [61]–=-=[63]-=-. This section begins with a review of the long-channel MOS noise model followed by a discussion of some recently proposed noise models for short-channel MOS devices. Long-Channel MOS Noise Model. Sin... |

14 |
A 1.5 GHz highly linear CMOS downconversion mixer
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Citation Context ...e any flicker noise due to the absence of current, and thus passive mixers are potentially attractive for use in direct-conversion receivers. Low power consumption and excellent linearity performance =-=[80]-=- are two additional advantages of passive mixers. However, both of these advantages are negated if an additional amplifier is needed to compensate for the conversion loss of the passive mixer. 184 IF ... |

13 |
Silicon Processing for the VLSI Era Volume 3 : The Submicron MOSFET
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Citation Context ...or this calculation, it is assumed that IsTe ⎡ E( y) ⎤ = ⎢1 + ⎥ T ⎣ Esat ⎦ ⎡ I D = ⎢1 + ⎣ g( V ) E Substituting (6.22) and (6.23) into (6.19) gives D 1 2 γ = 2 ∫ µ eff C g L I µ = In strong inversion =-=[66]-=-, I do D 2 2 eff Cox 2 g doL D = I W I V Dsat V D 0 2 D V D 2 ox ⎡ ⎢( V ⎣ W GS 2 ( V −V ) t GS 144 2 2 sat − ( V 2 ⎤ ⎥ ⎦ 2 −V −V ) dV t GS . −V ) V t D 1 + V 3 2 D ⎤ ⎥. ⎦ (6.23) (6.24) 2 1 ( VGS −Vt )... |

13 |
A practical method of designing rc active filters,” IRE Transaction on Circuit Theory
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Citation Context ...brief discussion of each of these analog filtering techniques follows. Sallen and Key Filter. A block diagram of a Sallen and Key section based on an amplifier with gain K is illustrated in Fig. 6.38 =-=[82]-=-, [21]. The voltage transfer function is given by V V a out 0 = (6.132) 2 in s + a1s + a0 187 KsV in where a0 and a1 are given by, respectively, R 1 1 a 0 = (6.133) R R C C 1 2 188 1 2 1 1 1 a1 = + + ... |

12 | A 2.4-GHz CMOS receiver for IEEE 802.11 wireless LAN’s
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Citation Context ...hitecture Due to its simplicity and potential for high integration, the direct-conversion architecture (Fig. 2.7) is the most promising candidate for implementing the receiver for the proposed system =-=[46]-=-, [47]. As discussed in Sections 2.3.1 and 2.3.2, receiver implementations based on the direct-conversion architecture must contend with dc offsets and flicker noise. Although the low-IF architecture ... |

12 |
A lowpower CMOS chipset for spread-spectrum communications
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Citation Context ...Ls ⎤ ⎥ ⎦ (6.99) Local shunt feedback LNA. A fourth topology which may be used to achieve a 50-Ω input resistance is based on a single transistor with local shunt feedback as illustrated in Fig. 6.14a =-=[67]-=-. The input impedance of this LNA is Z R l in R f + Rl = . (6.100) + g R + ( R + R )( g + jω C ) 1 m l f l g gs A narrowband input match may be achieved by adding a shunt inductor at the input of the ... |

12 |
Low-Power Sigma-Delta Modulators for RF Baseband Channel Applications
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Citation Context ...n Fig. 6.54. The device sizes and bias points of each amplifier are optimized for minimum power consumption. Power consumption in the Σ∆ ADCs is further reduced by using capacitive scaling techniques =-=[97]-=-. However, the presence of parasitic capacitances limits the achievable power savings resulting from this approach. The capacitor values and bias current of each of the four integrators are summarized... |

11 | Tradeoffs of performance and single chip implementation of indoor wireless multi-access receivers. Available on the World Wide Web at http://bwrc.eecs.berkeley.edu/Publications/1999/ tradeoffs performance singlechip implement/index.htm
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Citation Context ...tionality onto a single chip. In particular, advanced signal processing algorithms are very amenable to low-power digital design techniques and promise increased capacity along with higher data rates =-=[5]-=-. However, the performance of these algorithms may ultimately be limited by analog circuit impairments, such as noise, distortion, and mismatch. By accounting for analog impairments during the earlies... |

11 |
Modeling sigma-delta modulator non-idealities
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Citation Context ...similar since they are based on similar building blocks, such as switched-capacitor circuits and comparators. The structural model of a first-order sigma-delta (Σ∆) converter is described below [32], =-=[33]-=- as an example and similar techniques can be used to develop structural models for other types of ADCs. The block diagram of a first-order Σ∆ converter is illustrated in Fig. 4.17. The integrator is i... |

11 |
Low-power Low-voltage Analog-to-digital Conversion Techniques Using Pipelined Architectures
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(Show Context)
Citation Context ...MHz and a resolution of at least 7 bits. 6.7.1 Pipeline Architecture For these specifications, one possible approach of implementing the ADC is to use a pipeline architecture illustrated in Fig. 6.51 =-=[92]-=-. In this architecture, each of the N stages samples the signal from the previous stage and quantizes it to B bits. The quantized signal is then subtracted from the input signal and the result is ampl... |