## Closed form solution to simultaneous buffer insertion/sizing and wire sizing (1997)

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Venue: | IN PROC. INT. SYMP. ON PHYSICAL DESIGN |

Citations: | 46 - 5 self |

### BibTeX

@INPROCEEDINGS{Chu97closedform,

author = {Chris C. N. Chu and D. F. Wong},

title = {Closed form solution to simultaneous buffer insertion/sizing and wire sizing},

booktitle = {IN PROC. INT. SYMP. ON PHYSICAL DESIGN},

year = {1997},

pages = {192--197},

publisher = {}

}

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### Abstract

In this paper, we consider the delay minimization problem of a wire by simultaneously considering buffer insertion, buffer sizing and wire sizing. We consider three versions of the problem, namely using no buffer, using a given number of buffers, and using optimal number of buffers. We provide elegant closed form optimal solutions for all these versions.

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Citation Context ...apacitance. r0: Unit wire resistance. c0: Unit wire area capacitance. cg: Unit gate capacitance of bu er. rg: Unit gate resistance of bu er. cd: Unit di usion capacitance of bu er. Elmore delay model =-=[10]-=- is used here for delay calculation. A wire segment is modeled as a -type RC circuit as shown in Figure 2. A bu er is modeled as a switch-level RC circuit as shown in Figure 3. r l / h h l 0 c0l h 2 c... |

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Citation Context ... delay has become the dominant factor in deep submicron design. Recently, many works have been done on bu er insertion, bu er sizing and/or wire sizing in order to reduce the interconnect delay (e.g. =-=[1, 2, 3, 4, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16]-=- ). Currently, the best solutions to the bu er insertion, bu er sizing and/or wire sizing problems are either iterative algorithms which locally optimize the size of a wire segment or the size of a bu... |

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Citation Context ... delay has become the dominant factor in deep submicron design. Recently, many works have been done on bu er insertion, bu er sizing and/or wire sizing in order to reduce the interconnect delay (e.g. =-=[1, 2, 3, 4, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16]-=- ). Currently, the best solutions to the bu er insertion, bu er sizing and/or wire sizing problems are either iterative algorithms which locally optimize the size of a wire segment or the size of a bu... |

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Citation Context ... delay has become the dominant factor in deep submicron design. Recently, many works have been done on bu er insertion, bu er sizing and/or wire sizing in order to reduce the interconnect delay (e.g. =-=[1, 2, 3, 4, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16]-=- ). Currently, the best solutions to the bu er insertion, bu er sizing and/or wire sizing problems are either iterative algorithms which locally optimize the size of a wire segment or the size of a bu... |

33 |
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Citation Context ...his section, we use the parameters of the 0.18 µm technology listed in Cong and Pan [1998], which is based on the 1997 National Technology Roadmap for Semiconductors (NTRS’97) [Semiconductor Industry =-=Association 1997-=-]. The values are shown in Table I. Buffers of size 200 × minimum device are used both as driver and as load. 7.1 Generalization of Previous Results We observe that several previous results are specia... |

12 | Optimal shape function for a bidirectional wire under Elmore delay model - GAO, WONG - 1997 |

10 |
Fast performance-driven optimization for bu ered clock trees based on Lagrangian relaxation
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8 |
Bu er placement in distributed RC-tree networks for minimal Elmore delay
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7 |
Simultaneous bu er and wire sizing for performance and power optimization
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6 |
Closed form solution to simultaneous bu er insertion/sizing and wire sizing
- Chu, Wong
- 1997
(Show Context)
Citation Context ...fringing capacitance. Many proofs in this paper contain a lot of tedious manipulation of complicated mathematical expressions and so only proof outlines are given due to space limitation. Please read =-=[5]-=- for proof details. The following are the notations of the electrical parameters used in this paper: RD: Driver resistance. CL: Load capacitance. r0: Unit wire resistance. c0: Unit wire area capacitan... |

6 | A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing - Chu, Wong - 1998 |

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5 |
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(Show Context)
Citation Context ...t delay has become the dominant factor in deep submicron design. Recently, manyworks have been done on bu er insertion, bu er sizing and/or wire sizing in order to reduce the interconnect delay (e.g. =-=[1, 2, 3, 4, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16]-=- ). Currently, the best solutions to the bu er insertion, bu er sizing and/or wire sizing problems are either iterative algorithms which locally optimize the size of a wire segment or the size of a bu... |

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4 |
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1 | 2001. • CHU and Wong - CHEN, WONG |

1 | EWA: Efficient Wire-Sizing Algorithm - KAY, BUCHEUV, et al. - 1997 |

1 | 2001. Form Solution to Buffer Insertion • 371 - MENEZES, PULLELA, et al. |