Design of Low Noise, Low Power Linear CMOS Image Sensors

Design of Low Noise, Low Power Linear CMOS Image Sensors (2001)

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by Pavan Kumar Hanumolu , Prof John , Mcneill Prof , Len Polizzotto , Prof Donald Brown

BibTeX

@MISC{Hanumolu01designof,
    author = {Pavan Kumar Hanumolu and Prof John and Mcneill Prof and Len Polizzotto and Prof Donald Brown},
    title = {Design of Low Noise, Low Power Linear CMOS Image Sensors},
    year = {2001}
}

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Abstract

The implementation of active pixel based image sensors in CMOS technology is becoming increasingly important forproducing imaging systems that can be manufactured with low cost, low power, simple interface, and with good image quality. The major obstacle in the design of CMOS imagers is Fixed Pattern Noise (FPN) and Signal-to-Noise-Ratio (SNR) of the video output. This research focuses on minimizing FPN and improving SNR in linear CMOS image sensors which are needed in scanning and swiping applications such as nger print sensing, spectroscopy, and medical imaging systems. FPN is reduced in this research through the use of closed loop operational ampli ers in active pixels and through performing Correlated Double Sampling (CDS). SNR is improved by increasing the pixel saturation voltage. This thesis concludes that FPN can be reduced using the closed loop opamp bu ers. The major FPN noise sources are the shot noise from the photodiode, kTC noise from the sampling capacitors, and o set mismatches in the sample and hold ampli ers all of which are not compensated by CDS. Sample and hold ampli er o set mismatch is identi ed as

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