## Automatic synthesis of burst-mode asynchronous controllers (1995)

### Cached

### Download Links

Citations: | 69 - 10 self |

### BibTeX

@MISC{Nowick95automaticsynthesis,

author = {Steven Mark Nowick},

title = {Automatic synthesis of burst-mode asynchronous controllers},

year = {1995}

}

### Years of Citing Articles

### OpenURL

### Abstract

Asynchronous design has enjoyed a revival of interest recently, as designers seek to eliminate penalties of traditional synchronous design. In principle, asynchronous methods promise to avoid overhead due to clock skew, worst-case design assumptions and resynchronization of asynchronous external inputs. In practice, however, many asynchronous design methods suffer from a number of problems: unsound algorithms (implementations may have hazards), harsh restrictions on the range of designs that can be handled (single-input changes only), incompatibility with existing design styles and inefficiency in the resulting circuits. This thesis presents a new locally-clocked design method for the synthesis of asynchronous controllers. The method has been automated, is proven correct and produces high-performance implementations which are hazard-free at the gate-level. Implementations allow multiple-input changes and handle a relatively unconstrained class of behaviors (called "burst-mode" specifications). The method produces state-machine implementations with a minimal or near-minimal number of states. Implementations can be easily built in such common VLSI design styles as gate-array, standard cell and full-custom. Realizations typically have the latency of

### Citations

3843 |
Introduction to Automata Theory, Languages and Computability
- Hopcroft, Ullman, et al.
- 2001
(Show Context)
Citation Context ...b+ / x+ y+ c+ / xc- / x+ yb- / x- y+ a- / yFigure 3.1: Simple example specification. are useful in specifying the graph. First, for any set S, define the power set P(S) as the set of all subsets of S =-=[43]-=-. Using this notation, transi : E ! P(I) defines the set of input changes (or input burst) and transo : E ! P(O) defines the set of output changes (or output burst) for each edge in the graph. Intuiti... |

3409 | Communicating Sequential Processes
- Hoare
(Show Context)
Citation Context ...guage of concurrency [12, 55, 14, 33, 95, 3]. The program is compiled into an asynchronous circuit by a series of transformations. In Martin's method [55, 57], specifications are based on Hoare's CSP =-=[42]-=-. A specification describes a set of concurrent processes which communicate on channels. The description is transformed, through a series of steps, into a collection of gates and components which comm... |

361 |
Logic Minimization Algorithms for VLSI Synthesis
- Brayton
- 1984
(Show Context)
Citation Context ...ogic minimization problem. Step 3: Generate a Minimum Cover The dhf-prime implicant table is solved in three steps, using simple standard techniques. More sophisticated techniques can also be applied =-=[81, 7, 60]-=-. First, essential dhf-prime implicants are extracted using standard techniques. Second, the flow table is iteratively reduced. Rows and columns of the table may be removed using row-dominance and col... |

247 |
Trace theory for automatic hierarchical verification of speed-independent circuits
- Dill
- 1989
(Show Context)
Citation Context ...ounded gate and wire model is assumed. The concept of a delay-insensitive circuit is based on work of Clark and Molnar on Macromodules [22]. Formalizations have been described by Udding [90] and Dill =-=[32]-=-. Few practical DI circuits can be built from simple gates [56]; however, useful circuits can be built from more complex components [33, 44]. A speed-independent (SI) circuit is one which functions co... |

200 |
Synthesis of self-timed VLSI circuits from graph-theoretic specifications
- Chu
- 1987
(Show Context)
Citation Context ...ry concurrent behavior in hardware. Behaviors described by a net are determined using a reachability analysis. These behaviors are transformed into a more explicit representation called a state graph =-=[19]-=-. The state graph indicates the desired functionality of the implementation, and can be mapped into hardware. Several simple notations are based on a constrained class of Petri-nets called marked grap... |

161 |
Asynchronous Sequential Switching Circuits. WileyInterscience
- Unger
- 1969
(Show Context)
Citation Context ...nstead, they operate under distributed control. Asynchronous systems promise to avoid many of these problems by eliminating the global clock. However, in spite of much research over the last 40 years =-=[91]-=-, asynchronous designs are notoriously difficult to build. Problems with Asynchronous Design Most of the problems with asynchronous design center around the phenomenon of hazards, or potential glitche... |

159 |
Net Theory and the Modeling of Systems
- Petri
- 1981
(Show Context)
Citation Context ...ace behavior to fit into fixed protocols (e.g. 2- or 4-phase handshaking). Petri-net and Graph-Based Methods An alternative approach in asynchronous synthesis is to specify behavior using a Petri net =-=[77]-=-. A Petri-net is a compact graphical notation which can describe both concurrency and choice between events. A Petri-net has two types of vertices: places and transitions. Initially, tokens are assign... |

155 |
Programming in VLSI: From Communicating Processes to Delay-Insensitive Circuits
- Martin
- 1990
(Show Context)
Citation Context ...h a specification as a program in a high-level language of concurrency [12, 55, 14, 33, 95, 3]. The program is compiled into an asynchronous circuit by a series of transformations. In Martin's method =-=[55, 57]-=-, specifications are based on Hoare's CSP [42]. A specification describes a set of concurrent processes which communicate on channels. The description is transformed, through a series of steps, into a... |

136 | Performance Analysis and Optimization of Asynchronous Circuits - Burns - 1991 |

113 | The limitations to delay-insensitivity in asynchronous circuits - MARTIN - 1990 |

112 |
Multiple-Valued Minimization for PLA Optimization
- Rudell, Sangiovanni-Vincentelli
- 1987
(Show Context)
Citation Context ...f-prime implicants for function f are generated in two steps. The first step generates the prime implicants of f from the req-set (which defines the on-set) and the off-set, using standard techniques =-=[81, 82]-=-. The second step transforms these prime implicants into dhf-prime implicants using algorithm PI-to-DHF-PI. This algorithm is a simpler version of Algorithm B in [35]. The algorithm iteratively refine... |

111 |
Compiling communicating processes into delay-insensitive VLSI circuits
- Martin
- 1986
(Show Context)
Citation Context ...(ii) Petri-net, or graph-based, methods; and (iii) asynchronous state machines. Translation Methods Translation methods begin with a specification as a program in a high-level language of concurrency =-=[12, 55, 14, 33, 95, 3]-=-. The program is compiled into an asynchronous circuit by a series of transformations. In Martin's method [55, 57], specifications are based on Hoare's CSP [42]. A specification describes a set of con... |

84 |
Anomalous behavior of synchronizer and arbiter circuits
- Chaney, Molnar
- 1973
(Show Context)
Citation Context ...blem when attempting to synchronize inputs which can arrive at arbitrary times. Such inputs may cause synchronous storage elements to enter into undefined states. This problem is called metastability =-=[17]-=-. No known method exists to eliminate metastability. However, the probability of entering a metastable state is significantly reduced by using a pair of storage elements to "resynchronize" an asynchro... |

84 | Synthesis of timed asynchronous circuits - Myers, Meng - 1993 |

83 |
Logic Synthesis for VLSI Design
- Rudell
- 1989
(Show Context)
Citation Context ...dered which depend on bounded delay assumptions for correct operation, or which use added delay elements to fix or filter out glitches. 2.2 Definitions The following definitions are taken from Rudell =-=[81, 82]-=- with minor modifications (see also [7, 60]). Only single-output functions having binary input and output variables are 23sCHAPTER 2. COMBINATIONAL CIRCUITS AND HAZARDS 24 considered. Define sets P = ... |

81 |
The design of an asynchronous microprocessor
- Martin, Burns, et al.
- 1989
(Show Context)
Citation Context ...APTER 1. INTRODUCTION 7 Williams [100]. Several of the controller design methods described below are also used for datapath synthesis. Asynchronous microprocessors have been designed by Martin et al. =-=[58]-=- and Brunvand [11]. Other approaches include Dean's STRiP processor [30], and work by David, Ginosar and Yoeli [24], Ginosar and Michell [37] and Unger [94]. 1.2.4 Asynchronous Controllers There have ... |

77 |
Automatic gate-level synthesis of speed-independent circuits
- Beerel, Meng
- 1992
(Show Context)
Citation Context ...nts to eliminate hazards. However, the method does not demonstrate freedom from dynamic hazards (glitches which can occur when an output is changing value). An alternative approach by Beerel and Meng =-=[5]-=- is to synthesize speed-independent circuits directly from state graphs. This method avoids many of the syntactic requirements of STGs. Though the method produces hazard-free gate-level implementation... |

77 | Synthesis of Hazard-Free Asynchronous Circuits with Bounded Wire Delays
- Lavagno, Keutzer, et al.
- 1995
(Show Context)
Citation Context ...ination for two-level combinational logic. This method has been successfully applied to a number of small circuits, but in general is not guaranteed to succeed. Lavagno describes a promising approach =-=[47, 49]-=- to synthesizing gate-level hazard-free circuits from STGs. The method requires the use of added delay elements to eliminate hazards. However, the method does not demonstrate freedom from dynamic haza... |

77 |
NOVA: state assignment of finite state machines for optimal two-level implementation
- Villa
- 1990
(Show Context)
Citation Context ... state assignment, as in a synchronous design. There is no need to use a critical race-free state assignment. Therefore, state encoding can be performed using standard synchronous tools, such as nova =-=[99]-=-. However, there is a slight mismatch between nova and our design style. nova attempts to find an optimal state encoding, that is, one which leads to a minimal logic implementation in sum-of-products ... |

69 |
Logic Design Principles: With Emphasis on Testable Semicustom Circuits, Prentice-Hall, Englewood Cliffs, NJ
- McCluskey
- 1986
(Show Context)
Citation Context ... to eliminate metastability. However, the probability of entering a metastable state is significantly reduced by using a pair of storage elements to "resynchronize" an asynchronous input to the clock =-=[60]-=-. However, such resynchronization results in a performance loss. Worst-Case Design. Synchronous designs have difficulty taking advantage of datadependent processing delays. If a component can process ... |

66 |
Signal graphs: From self-timed to timed ones
- Rosenblum, Yakovlev
- 1985
(Show Context)
Citation Context ...pped into hardware. Several simple notations are based on a constrained class of Petri-nets called marked graphs: Seitz's M-Nets [83], Molnar's I-Nets [67], and Rosenblum and Yakovlev's Signal Graphs =-=[80]-=-. These nets model concurrency between events, but cannot describe conditional behavior, such as a choice between inputs. Chu proposed a more general notation called Signal Transition Graphs [19], or ... |

65 | Exact two-level minimization of hazard-free logic with multiple-input changes
- Nowick, Dill
- 1992
(Show Context)
Citation Context ...is chapter represents joint work with Mark E. Dean. The goal of this chapter is to demonstrate the effectiveness of our synthesis method for the design of real-world systems. Most previous work by us =-=[73, 72, 74]-=- and others has focused on detailed algorithms for design methods and their application to fairly small examples. Furthermore, realistic quantitative comparisons between asynchronous and synchronous d... |

62 |
Automatic synthesis of asynchronous circuits from high-level specifications
- Meng, Brodersen, et al.
- 1989
(Show Context)
Citation Context ...ms. This requirement is called the complete state coding (CSC) property by Moon et al. [68]. A more restrictive requirement is called the unique state coding (USC) property by Vanbekbergen [96]. Meng =-=[64, 65]-=- extended this work, developing a complete automated synthesis system. As in Chu's method, arcs may need to be added to an STG before a circuit can be synthesized. However, Meng's algorithms add these... |

60 |
Self-timed rings and their application to division
- Williams
- 1991
(Show Context)
Citation Context ...stem operates under nominal conditions, performance is limited by worst-case design assumptions. In practice, the cumulative "derating" of system performance based on these factors can be significant =-=[30, 100]-=-. Dean [30] indicates that, if such design-for-worst-case could be avoided, many systems would actually run almost twice as fast on average. Power Consumption. At a time when designers are increasingl... |

55 |
Automatic Synthesis of Locally-Clocked Asynchronous State Machines
- Nowick, Dill
- 1991
(Show Context)
Citation Context ... dhf-prime implicant table and solves it (Steps 2 and 3). This logic minimization program has been used as the the final component in the locally-clocked synthesis method for asynchronous controllers =-=[72]-=-. It has recently been incorporated into another synthesis method as well[106]. Both methods produce combinational functions which are guaranteed by construction to have hazard-free two-level implemen... |

54 |
Synthesis of asynchronous state machines using a local clock
- Nowick, Dill
- 1991
(Show Context)
Citation Context ...is chapter represents joint work with Mark E. Dean. The goal of this chapter is to demonstrate the effectiveness of our synthesis method for the design of real-world systems. Most previous work by us =-=[73, 72, 74]-=- and others has focused on detailed algorithms for design methods and their application to fairly small examples. Furthermore, realistic quantitative comparisons between asynchronous and synchronous d... |

54 |
D.: Optimized synthesis of asynchronous control circuits from graph-theoretic specifications
- Vanbekbergen, Catthoor, et al.
- 1990
(Show Context)
Citation Context ...ment problems. This requirement is called the complete state coding (CSC) property by Moon et al. [68]. A more restrictive requirement is called the unique state coding (USC) property by Vanbekbergen =-=[96]-=-. Meng [64, 65] extended this work, developing a complete automated synthesis system. As in Chu's method, arcs may need to be added to an STG before a circuit can be synthesized. However, Meng's algor... |

53 |
Translating concurrent programs into delayinsensitive circuits
- Brunvand, Sproull
- 1989
(Show Context)
Citation Context ...(ii) Petri-net, or graph-based, methods; and (iii) asynchronous state machines. Translation Methods Translation methods begin with a specification as a program in a high-level language of concurrency =-=[12, 55, 14, 33, 95, 3]-=-. The program is compiled into an asynchronous circuit by a series of transformations. In Martin's method [55, 57], specifications are based on Hoare's CSP [42]. A specification describes a set of con... |

53 | The Post Office experience: Designing a large asynchronous chip
- Coates, Davis, et al.
- 1993
(Show Context)
Citation Context ...27]. More recently, Davis, Coates and Stevens have developed an automated synthesis system at HP Laboratories [26]. The system has been used to design controllers for an asynchronous Post Office chip =-=[29, 86]-=-. The method produces high-performance implementations; however, it relies on a verifier [32] to guarantee hazard-free designs. Self-Synchronized Machines. The difficulty and overhead of hazard-elimin... |

53 |
Synthesis of delay-insensitive modules
- Molnar, Fang, et al.
- 1985
(Show Context)
Citation Context ...unctionality of the implementation, and can be mapped into hardware. Several simple notations are based on a constrained class of Petri-nets called marked graphs: Seitz's M-Nets [83], Molnar's I-Nets =-=[67]-=-, and Rosenblum and Yakovlev's Signal Graphs [80]. These nets model concurrency between events, but cannot describe conditional behavior, such as a choice between inputs. Chu proposed a more general n... |

50 |
A formal approach to designing delay-insensitive circuits
- Ebergen
- 1991
(Show Context)
Citation Context ...22]. Formalizations have been described by Udding [90] and Dill [32]. Few practical DI circuits can be built from simple gates [56]; however, useful circuits can be built from more complex components =-=[33, 44]-=-. A speed-independent (SI) circuit is one which functions correctly regardless of gate delays; wires are assumed to have negligible or zero-delay. The original formulation of SI circuits is due to Dav... |

47 | detection in combinational and sequential switching circuits,” IBM Journal - Eichelberger, “Hazard - 1965 |

46 |
The design of a self-timed circuit for distributed mutual exclusion
- MARTIN
- 1985
(Show Context)
Citation Context ... automated by Burns [16], who has also developed techniques to analyze and improve circuit performance [15]. The method has been applied to a number of designs: a distributed mutual exclusion element =-=[54]-=-, a multiply-accumulate unit [70], an asynchronous microprocessor [58], and several other controllers [14]. Designs typically assume communication using a four-phase handshaking protocol. In four-phas... |

43 |
Translating Concurrent Communicating Programs into Asynchronous Circuits
- Brunvand
- 1991
(Show Context)
Citation Context ...en speedindependent and delay-insensitive designs in the circuit hierarchy, and are called quasidelay-insensitive [15].sCHAPTER 1. INTRODUCTION 8 A similar approach, developed by Brunvand and Sproull =-=[12, 10]-=-, uses a variant of CSP, called occam, to describe a concurrent system. In this method, an occam description is first compiled into an unoptimized circuit using syntax-directed translation. The circui... |

43 |
A method for minimizing the number of internal states in incompletely specified sequential networks
- Grasselli, Luccio
- 1965
(Show Context)
Citation Context ...state minimization is to find a minimal closed cover for a given flow table. Grasselli and Luccio developed a general algorithm to produce a minimal closed cover, which makes use of prime compatibles =-=[40]-=-. Grasselli also developed an algorithmsCHAPTER 3. LOCALLY-CLOCKED ASYNCHRONOUS STATE MACHINES 87 to produce minimal closed partitions, using admissible compatibles [39]. Our algorithm follows a simpl... |

41 | A generalized state assignment theory for transformations on signal transition graphs - Vanbekbergen, Lin, et al. - 1992 |

38 | Hazard-non-increasing gate-level optimization algorithms
- Kung
- 1992
(Show Context)
Citation Context ...mations. Multi-level transformations which introduce no hazards into a combinational network are described by Unger [91]. Recently, this set of transformations has been significantly extended by Kung =-=[45]-=-. The final step in logic synthesis is technology mapping, or the mapping of combinational logic to components in a given cell library. Traditional technology mapping may introduce hazardous behavior ... |

38 | Synthesis of 3D asynchronous state machines
- Yun, Dill, et al.
- 1992
(Show Context)
Citation Context ...arises in many asynchronous sequential applications. The method has been incorporated into synthesis programs for two distinct asynchronous design styles: the locally-clocked method and the 3D method =-=[106]-=-. 107sCHAPTER 4. EXACT HAZARD-FREE TWO-LEVEL LOGIC MINIMIZATION 108 4.1.1 Two-Level Hazard-Free Logic Minimization Problem The two-level hazard-free logic minimization problem can be stated as follows... |

33 | Practical asynchronous controller design
- Nowick, Yun, et al.
- 1992
(Show Context)
Citation Context ...un on a set of examples. The largest example is a cache controller having 20 inputs and 19 outputs (dean-ctrl) [71]. The program was also run on two SCSI controller designs (oscsi-ctrl and scsi-ctrl) =-=[75]-=-. Table 4.4 describes the results of Algorithm PI-to-DHF-PI. The algorithm transforms prime implicants into dhf-prime implicants. Prime implicants which contain only don'tcare minterms are not include... |

32 |
Macromodular computer systems
- Clark
- 1967
(Show Context)
Citation Context ...ons correctly regardless of gate and wire delays. That is, an unbounded gate and wire model is assumed. The concept of a delay-insensitive circuit is based on work of Clark and Molnar on Macromodules =-=[22]-=-. Formalizations have been described by Udding [90] and Dill [32]. Few practical DI circuits can be built from simple gates [56]; however, useful circuits can be built from more complex components [33... |

32 | Introduction to the Theory of Switching Circuits - McCluskey - 1965 |

32 |
Automatic technology mapping for generalized fundamental-mode asynchronous designs
- Siegel, Micheli, et al.
- 1993
(Show Context)
Citation Context ...c network. Algorithms must be used which insure that the mapping of the circuit into library cells does not introduce hazards. Such technology mapping algorithms have been developed by Siegel, et al. =-=[84]-=-.sCHAPTER 4. EXACT HAZARD-FREE TWO-LEVEL LOGIC MINIMIZATION 128 4.11 Conclusions This chapter considers the two-level hazard-free minimization problem for several reasons: the general problem has not ... |

31 |
Synchronization Design for Digital Systems
- Meng
- 1990
(Show Context)
Citation Context ... A micropipeline consists of alternating computation stages separated by storage elements and control circuitry. Asynchronous datapaths have been designed for multiplication [70], division [101], DSP =-=[65]-=- and other applications [50] (see references in [100]). Micropipelines have been generalized to ring [100] and multi-ring structures [85]. Techniques to eliminate overhead between stages have been dev... |

31 |
Internal state assignments for asynchronous sequential machines
- Tracey
- 1966
(Show Context)
Citation Context ...ine may stabilize in an incorrect transient state instead of the next state. In this case, a critical race occurs. This problem can be avoided by using one-hot [91], one-shot [91], Liu [52] or Tracey =-=[89]-=- critical-race free state codes. In general these codes require extra state bits. In addition, logic hazards may occur during a state change. One common approach is to tolerate output hazards. Much of... |

30 |
Solving the state assignment problem for signal transition graphs
- Lavagno, Moon, et al.
- 1992
(Show Context)
Citation Context ...es to add state variables. This step can be thought of as state minimization and state assignment [60].sCHAPTER 1. INTRODUCTION 11 Progress in this area has been made in recent work by Lavagno et al. =-=[48]-=- and Vanbekbergen et al. [97]. In general, though, because of the need for critical race-free codes (discussed further below), state assignments for STGs may require the use of more state variables th... |

29 | SHILPA: A high-level synthesis system for self-timed circuits
- Akella, Gopalakrishnan
- 1992
(Show Context)
Citation Context ...(ii) Petri-net, or graph-based, methods; and (iii) asynchronous state machines. Translation Methods Translation methods begin with a specification as a program in a high-level language of concurrency =-=[12, 55, 14, 33, 95, 3]-=-. The program is compiled into an asynchronous circuit by a series of transformations. In Martin's method [55, 57], specifications are based on Hoare's CSP [42]. A specification describes a set of con... |

26 |
Synthesis of hazard-free asynchronous circuits from graphical speci cations
- Moon, Stephan, et al.
- 1991
(Show Context)
Citation Context ...ncy of the net. Also, state variables may need to be added explicitly in the net to avoid state assignment problems. This requirement is called the complete state coding (CSC) property by Moon et al. =-=[68]-=-. A more restrictive requirement is called the unique state coding (USC) property by Vanbekbergen [96]. Meng [64, 65] extended this work, developing a complete automated synthesis system. As in Chu's ... |

26 |
Delay-insensitive codes - an overview
- Verhoeff
- 1988
(Show Context)
Citation Context ...e can be a subset of another, since otherwise the behavior may be ambiguous (cf.sCHAPTER 3. LOCALLY-CLOCKED ASYNCHRONOUS STATE MACHINES 39 the more general requirements for delay-insensitive codes in =-=[98]-=-). This restriction is called the maximal set property. Second, a given state is always entered with the same set of input values; that is, each state has a unique entry point (this restriction simpli... |

24 | Syntax-directed translation of concurrent programs into self-timed circuits
- Burns, Martin
- 1988
(Show Context)
Citation Context ...municate on channels. The description is transformed, through a series of steps, into a collection of gates and components which communicate on wires. The synthesis method has been automated by Burns =-=[16]-=-, who has also developed techniques to analyze and improve circuit performance [15]. The method has been applied to a number of designs: a distributed mutual exclusion element [54], a multiply-accumul... |

24 |
An overview of DI algebra
- Josephs, Udding
- 1993
(Show Context)
Citation Context ...22]. Formalizations have been described by Udding [90] and Dill [32]. Few practical DI circuits can be built from simple gates [56]; however, useful circuits can be built from more complex components =-=[33, 44]-=-. A speed-independent (SI) circuit is one which functions correctly regardless of gate delays; wires are assumed to have negligible or zero-delay. The original formulation of SI circuits is due to Dav... |