Logarithmic Delay for N × N Packet Switches (2004)
| Venue: | IEEE WORKSHOP ON HIGH PERFORMANCE SWITCHING AND ROUTING — APRIL 2004 |
| Citations: | 1 - 0 self |
BibTeX
@MISC{Neely04logarithmicdelay,
author = {Michael J. Neely and Eytan Modiano},
title = { Logarithmic Delay for N × N Packet Switches},
year = {2004}
}
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Abstract
We consider the fundamental delay bounds for scheduling packets in an N × N packet switch operating under the crossbar constraint. Algorithms that make scheduling decisions without considering queue backlog are shown to incur an average delay of at least O(N). We then prove that O(log(N)) delay is achievable with a simple frame based algorithm that uses queue backlog information. This is the best known delay bound for packet switches, and is the first analytical proof that sublinear delay is achievable in a packet switch with random inputs. The algorithm is shown to be implementable with very low complexity, requiring O(N 1.5 log(N)) total operations per timeslot.
