• Documents
  • Authors
  • Tables
  • Other Seers ▼
    RefSeer AckSeer CollabSeer SeerSeer
  • Log in
  • Sign up
  • MetaCart

CiteSeerX logo

Advanced Search Include Citations
Advanced Search Include Citations | Disambiguate

Simultaneous Multithreading: Maximizing On-Chip Parallelism (1995)

Cached

  • Download as a PDF

Download Links

  • [www.cs.pitt.edu]
  • [www.cs.princeton.edu]
  • [www.cs.utah.edu]
  • [www.cs.utah.edu]
  • [www.cs.utah.edu]
  • [lazowska.cs.washington.edu]
  • [www.ece.ucdavis.edu]
  • [paul.rutgers.edu]
  • [impact.asu.edu]
  • [www.princeton.edu]
  • [www.cs.binghamton.edu]
  • [cardit.et.tudelft.nl]

  • Save to List
  • Add to Collection
  • Correct Errors
  • Monitor Changes
by Dean M. Tullsen , Susan J. Eggers , Henry M. Levy
Citations:623 - 46 self
  • Summary
  • Active Bibliography
  • Co-citation
  • Clustered Documents
  • Version History

BibTeX

@MISC{Tullsen95simultaneousmultithreading:,
    author = {Dean M. Tullsen and Susan J. Eggers and Henry M. Levy},
    title = { Simultaneous Multithreading: Maximizing On-Chip Parallelism},
    year = {1995}
}

Years of Citing Articles

Bookmark

citeulike Connotea Bibsonomy Del.icio.us Digg Reddit

OpenURL

 

Abstract

This paper examines simultaneous multithreading, a technique permitting several independent threads to issue instructions to a superscalar’s multiple functional units in a single cycle. We present several models of simultaneous multithreading and compare them with alternative organizations: a wide superscalar, a fine-grain multithreaded processor, and single-chip, multiple-issue multiprocessing architectures. Our results show that both (single-threaded) superscalar and fine-grain multithreaded architectures are limited in their ability to utilize the resources of a wide-issue processor. Simultaneous multithreading has the potential to achieve 4 times the throughput of a superscalar, and double that of fine-grain multithreading. We evaluate several cache configurations made possible by this type of organization and evaluate tradeoffs between them. We also show that simultaneous multithreading is an attractive alternative to single-chip multiprocessors; simultaneous multithreaded processors with a variety of organizations outperform corresponding conventional multiprocessors with similar execution resources. While simultaneous multithreading has excellent potential to increase processor utilization, it can add substantial complexity to the design. We examine many of these complexities and evaluate alternative organizations in the design space.

Citations

398 A study of branch prediction strategies - Smith - 1981
351 The Tera computer system - Alverson, Callahan, et al. - 1990
339 Limits of Instruction-Level Parallelism - Wall - 1991
254 APRIL: a processor architecture for multiprocessing - Agarwal, Lim, et al. - 1990
218 Limits of control flow on parallelism - Lam, Wilson - 1992
183 Architecture and applications of the HEP multiprocessor computer system - Smith - 1981
169 The Multiflow trace scheduling compiler - Lowney, Freudenberger, et al. - 1993
130 Multiprocessor Simulation and Tracing Using Tango - Davis, Goldschmidt, et al. - 1991
118 High-bandwidth data memory systems for superscalar processors - Sohi, Franklin - 1991
113 The Multiscalar Architecture - Franklin - 1993
111 Performance tradeoffs in multithreaded processors - Agarwal - 1992
110 The expandable split window paradigm for exploiting fine-grain parallelism - Franklin, Sohi - 1992
103 Comparative Evaluation of Latency Reducing and Tolerating Techniques - Gupta, Hennessy, et al. - 1991
99 Exploring the benefits of multiple hardware contexts in a multiprocessor architecture: preliminary results - Weber, Gupta - 1989
83 An elementary processor architecture with simultaneous instruction issuing from multiple threads - Hirata, Kimura, et al. - 1992
76 Processor coupling: Integrating compile time and runtime scheduling for parallelism - Keckler, Dally - 1992
71 Interleaving: A multithreading technique targeting multiprocessors and workstations - Laudon, Gupta, et al. - 1994
57 Eicken. Analysis of multithreaded architectures for parallel computing - Saavedra-Barrera, Culler, et al. - 1990
49 MASA: A multithreaded processor architecture for parallel symbolic computing - Halstead, Fujita - 1988
47 Some Efficient Architecture Simulation Techniques - Bedichek - 1990
46 dataflow subsume von Neumann computing - Can - 1989
40 The effectiveness of multiple hardware contexts - Thekkath, Eggers - 1994
32 New CPU benchmark suites from SPEC - Dixit - 1992
23 A benchmark evaluation of a multi-threaded RISC processor architecture - Prasadh, Wu - 1991
21 The concurrent execution of multiple instruction streams on superscalar processors - Torng - 1991
21 Performance estimation of multistreamed, superscalar processors - Yamamoto, Serrano, et al. - 1994
20 The PowerPC 604 - Song, Denman, et al. - 1994
14 M-Machine architecture v1.0 - Dally, Keckler, et al. - 1994
12 Nikhil and Arvind. Can Dataflow Subsume Von Neumann Computing - S - 1989
9 An overview of the 21164 AXP microprocessor - Edmondson, Rubinfield - 1994
7 Single instruction steam parallelism is greater than two - Butler, Yeh, et al. - 1991
6 The synergistic effect of thread scheduling and caching in multithreaded computers - McCrackin - 1993
6 The Multiflow trace scheduling compiler - Karzes, Lichtenstein, et al. - 1993
3 Low-power architecture - Dally - 2005
1 I31 [41 A. Aganval. Performance tradeoffs in multithreaded pmcessots - PI - 1992
1 Comparative evaluation of latency reducing and tolerating techniques - Gharachorloo, Mowty, et al. - 1991
1 An elementary processor architecture with simultaneous instruction iSSuinE from multiple threads - Nishizawa - 1992
1 Sixth lnrernor~onal Conference on Archrfecrural superscalar processors - In
1 Eicken. Analysis of multithreaded architectures for parallel computing - von - 1990
The National Science Foundation
  • About CiteSeerX
  • Submit Documents
  • Privacy Policy
  • Help
  • Data
  • Source
  • Contact Us

Developed at and hosted by The College of Information Sciences and Technology

© 2007-2010 The Pennsylvania State University