## Simultaneous voltage scaling and gate sizing for low-power design (2002)

Venue: | IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing |

Citations: | 6 - 0 self |

### BibTeX

@INPROCEEDINGS{Chen02simultaneousvoltage,

author = {Chunhong Chen and Majid Sarrafzadeh},

title = {Simultaneous voltage scaling and gate sizing for low-power design},

booktitle = {IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing},

year = {2002},

pages = {2002}

}

### OpenURL

### Abstract

Abstract—This paper presents a new approach using simultaneous voltage-scaling and gate-sizing for low power without violating the timing constraints. We provide the problem formulation in this application, and propose algorithms for single voltagescaling, single gate-sizing, and their simultaneous manipulation. We target a globally optimal solution by showing how the power optimization is related to the maximum-weighted-independent-set (MWIS) problem. Experimental results on a set of benchmark circuits show that the simultaneous voltage-scaling and gate-sizing generates maximum power reduction. The average power savings range from 23 % to 57 % over all tested circuits, depending upon the circuit topology, underlying gate library and specific supply voltages. Index Terms—Gate sizing, low power, simultaneous approach, voltage scaling. I.

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Citation Context ...res very expensive computation cost. Unlike the VS, gate sizing (GS) is a well-known technique which targets power optimization by reducing load capacitance. Several approaches have been explored [8]–=-=[12]-=-. In [9], for example, gate resizing was performed in two phases. The first phase carries out single gate resizing, and the second phase targets multiple gate resizing. Resizing a single gate at the e... |

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Citation Context ...expensive computation cost. Unlike the VS, gate sizing (GS) is a well-known technique which targets power optimization by reducing load capacitance. Several approaches have been explored [8]–[12]. In =-=[9]-=-, for example, gate resizing was performed in two phases. The first phase carries out single gate resizing, and the second phase targets multiple gate resizing. Resizing a single gate at the early sta... |

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Citation Context ...ingle gate resizing on slack variation decreases quickly by fanin/fanout level geometrically. Unfortunately, this observation is not true, especially when the gate lies on a long slack-sensitive path =-=[20]-=-. From a general point of view, reducing either the supply voltage or the physical size of a gate leads to a gate delay increase which implies the decreased slack time. In this sense, the VS and/or GS... |

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Citation Context ...alty, respectively, due to voltage scaling for gate , given as follows: and (5) (6) (7) (8) (9) Fig. 2. Calculation of weight functions for GS and VS. Similarly, we can have based on (5) and (6) (see =-=[28]-=- for more details). Intuitively, gates with high weight are better candidates for VS or GS. From (8) and (9), delay variation and power savings for gate due to the VS depend upon the parameters of gat... |

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Citation Context ...pth-first search from the primary outputs to find gates which may operate at a low-supply voltage without violating the timing constraints of the circuit. Some improvements on CVS have been made [4], =-=[19]-=-, but they lack a global view and do not consider the switching activity information which is linearly related to the dynamic power. A linear programming approach was proposed in [18] to address dual-... |

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Citation Context ...nsitions at internal nodes of gates for low power, the resulting power reduction is very limited. In this work, we relate the power optimization to the maximum-weighted-independent-set (MWIS) problem =-=[14]-=-. Algorithms for single VS, single GS, and simultaneous VS and GS are proposed to optimize power. Experiments show that simultaneous VS and GS obtain maximum power improvement. The improvement rate ra... |

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