Simultaneous voltage scaling and gate sizing for low-power design (2002)
| Venue: | IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing |
| Citations: | 4 - 0 self |
BibTeX
@INPROCEEDINGS{Chen02simultaneousvoltage,
author = {Chunhong Chen and Majid Sarrafzadeh},
title = {Simultaneous voltage scaling and gate sizing for low-power design},
booktitle = {IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing},
year = {2002},
pages = {2002}
}
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Abstract
Abstract—This paper presents a new approach using simultaneous voltage-scaling and gate-sizing for low power without violating the timing constraints. We provide the problem formulation in this application, and propose algorithms for single voltagescaling, single gate-sizing, and their simultaneous manipulation. We target a globally optimal solution by showing how the power optimization is related to the maximum-weighted-independent-set (MWIS) problem. Experimental results on a set of benchmark circuits show that the simultaneous voltage-scaling and gate-sizing generates maximum power reduction. The average power savings range from 23 % to 57 % over all tested circuits, depending upon the circuit topology, underlying gate library and specific supply voltages. Index Terms—Gate sizing, low power, simultaneous approach, voltage scaling. I.
