## Verification of analog/mixed-signal circuits using labeled hybrid petri nets (2006)

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Venue: | IN: PROC. OF ICCAD |

Citations: | 18 - 9 self |

### BibTeX

@INPROCEEDINGS{Little06verificationof,

author = {Scott Little and Nicholas Seegmiller and David Walter and Chris Myers and Tomohiro Yoneda},

title = { Verification of analog/mixed-signal circuits using labeled hybrid petri nets},

booktitle = {IN: PROC. OF ICCAD},

year = {2006},

pages = {275--282},

publisher = {Society Press}

}

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### Abstract

System on a chip design results in the integration of digital, analog, and mixed-signal circuits on the same substrate which further complicates the already difficult validation problem. This paper presents a new model, labeled hybrid Petri nets (LHPNs), that is developed to be capable of modeling such a heterogeneous set of components. This paper also describes a compiler from VHDL-AMS to LHPNs. To support formal verification, this paper presents an efficient zone-based state space exploration algorithm for LHPNs. This algorithm uses a process known as warping to allow zones to describe continuous variables that may be changing at variable rates. Finally, this paper describes the application of this algorithm to a couple of analog/mixed-signal circuit examples.

### Citations

386 | Hybrid Automata: An Algorithmic Approach to the Specification and Verification of Hybrid Systems
- Alur, Courcoubetis, et al.
- 1993
(Show Context)
Citation Context ...nge of Vout. The 276 3. LABELED HYBRID PETRI NETS An LHPN is a Petri net model developed to represent AMS circuits. The model is inspired by features in both hybrid Petri nets [6] and hybrid automata =-=[1]-=-. This model has also been developed in such a way that it can be easily generated from VHDL-AMS descriptions. An LHPN is a tuple N = 〈P, T, B, V, F, L, M0, S0, Q0, R0〉: • P : is a finite set of place... |

384 | H.: HYTECH: A model checker for hybrid systems
- Henzinger, Ho, et al.
- 1997
(Show Context)
Citation Context ...es with R = 200Ω in 0.84s after finding 115 state sets, and the property does not verify with R = 242Ω in 1.20s after finding 132 state sets. We also attempted this verification using the HyTech tool =-=[17]-=-, but it is unable to complete due to arithmetic overflow errors. HyTech can complete analysis with less precision on the rates, but the model of the circuit no longer produces oscillation. Therefore,... |

232 |
Timing assumptions and verification of finite-state concurrent systems
- Dill
- 1989
(Show Context)
Citation Context ...cessary to represent this infinite number of states using a finite number of state equivalence classes called state sets. Our analysis method uses zones defined using difference bound matrices (DBMs) =-=[7]-=- to represent the continuous portion of the state space. Our methodology is based upon one for analyzing timed systems [2,3] with extensions necessary to deal with continuous quantities changing at va... |

143 | PHAVer: Algorithmic verification of hybrid systems past HyTech
- Frehse
(Show Context)
Citation Context ...ant accuracy in the abstraction to a Boolean model. Frehse’s PHAVer model checker analyzes linear hybrid automata models of AMS circuits using convex polyhedra to represent the continuous state space =-=[8, 9]-=-. While these polyhedra can become quite complex, one unique feature of PHAVer is that it allows for performance to be tuned at the expense of a conservative state space. Previously, we developed a to... |

99 | Computer-aided verification
- Clarke, Kurshan
- 1996
(Show Context)
Citation Context ...lidation methods that can support the heterogeneous nature of SoC designs. Formal verification is a validation method that has shown advantages over simulation based methodologies for digital systems =-=[4]-=-. Based on this success there has recently been some research on applying formal verification based methods to AMS circuits [5, 8–16, 18, 21]. The major challenge in verifying AMS circuits is that con... |

50 |
Asynchronous Circuit Design
- Myers
- 2001
(Show Context)
Citation Context ...Q2 − + C2 C1 = 1 pF C2 = 25 pF Vout freq(Φ1) = freq(Φ2) = 500 kHz dVout/dt = ±(18 to 22) mV/µs process begins by assigning inc18 to ’1’ (this uses the assign function defined in the handshake package =-=[19]-=-) which starts Vout increasing at a rate of 18 mV/µs. After a randomly selected time period between 0 and 100 µs, it sets inc22 to ’1’ changing the rate of increase to 22 mV/µs. It then waits until th... |

38 | Verification of Analog and Mixed-Signal Circuits Using Hybrid System Techniques - Dang, Donze - 2004 |

37 |
Towards formal verification of analog designs
- Gupta, Krogh, et al.
- 2004
(Show Context)
Citation Context ...ptions by hand into a hybrid automata model. The remaining results in Table 1 are versions of the tunnel diode oscillator shown in Fig. 8 [13]. The numerical parameters used for this example are from =-=[11]-=-. The goal of verification is to ensure that Il oscillates for specific circuit parameters and initial conditions. Continuous variables in LHPNs can only change at constant rates. Therefore, to analyz... |

33 |
On Hybrid Petri Nets. Discrete Event Dynamic Systems: Theory and Applications
- David, Alla
- 2001
(Show Context)
Citation Context ... control the rate of change of Vout. The 276 3. LABELED HYBRID PETRI NETS An LHPN is a Petri net model developed to represent AMS circuits. The model is inspired by features in both hybrid Petri nets =-=[6]-=- and hybrid automata [1]. This model has also been developed in such a way that it can be easily generated from VHDL-AMS descriptions. An LHPN is a tuple N = 〈P, T, B, V, F, L, M0, S0, Q0, R0〉: • P : ... |

30 | Verifying Analog Oscillator Circuits Using Forward/Backward Abstraction Refinement
- Frehse, Krogh, et al.
(Show Context)
Citation Context ...ant accuracy in the abstraction to a Boolean model. Frehse’s PHAVer model checker analyzes linear hybrid automata models of AMS circuits using convex polyhedra to represent the continuous state space =-=[8, 9]-=-. While these polyhedra can become quite complex, one unique feature of PHAVer is that it allows for performance to be tuned at the expense of a conservative state space. Previously, we developed a to... |

17 | Timed State Space Exploration Using POSET’s
- Belluomini, Myers
- 2000
(Show Context)
Citation Context ...Our analysis method uses zones defined using difference bound matrices (DBMs) [7] to represent the continuous portion of the state space. Our methodology is based upon one for analyzing timed systems =-=[2,3]-=- with extensions necessary to deal with continuous quantities changing at variable rates. The state sets are represented with the tuple ψ = 〈M, S, Q, R, I, Z〉 where: • M ⊆ P is the set of marked place... |

17 | Model checking algorithms for analog verification
- Hartong, Hedrich, et al.
- 2002
(Show Context)
Citation Context ...dt = ±(16 to 24) mV/µs Figure 7: A non-saturating integrator. of change is assumed to be constant. This is accomplished using a differential equation discretization method similar to that proposed in =-=[12, 13]-=-. {(vout ≥ −2000) ∧ (vout ≤ 2000)} 〈fail := T 〉 Figure 6: An LHPN for the assert statement. t13 Vin R L Il C Vc With the addition of this assert statement, a deadlock is found during state space explo... |

16 | Timed circuit verification using TEL structures
- Belluomini, Myers
- 2001
(Show Context)
Citation Context ...Our analysis method uses zones defined using difference bound matrices (DBMs) [7] to represent the continuous portion of the state space. Our methodology is based upon one for analyzing timed systems =-=[2,3]-=- with extensions necessary to deal with continuous quantities changing at variable rates. The state sets are represented with the tuple ψ = 〈M, S, Q, R, I, Z〉 where: • M ⊆ P is the set of marked place... |

13 |
On discrete modeling and model checking for nonlinear analog systems
- Hartong, Hedrich, et al.
- 2002
(Show Context)
Citation Context ...dt = ±(16 to 24) mV/µs Figure 7: A non-saturating integrator. of change is assumed to be constant. This is accomplished using a differential equation discretization method similar to that proposed in =-=[12, 13]-=-. {(vout ≥ −2000) ∧ (vout ≤ 2000)} 〈fail := T 〉 Figure 6: An LHPN for the assert statement. t13 Vin R L Il C Vc With the addition of this assert statement, a deadlock is found during state space explo... |

12 | A formal approach to verification of linear analog circuits with parameter tolerances - Hedrich, Barke - 1998 |

12 |
Verification of analog and mixed-signal circuits using timed hybrid petri nets
- Little, Walter, et al.
- 2004
(Show Context)
Citation Context ...n algorithms for time/timed Petri nets to analyze hybrid Petri net models of AMS circuits using a process known as warping that normalizes the advancement of all continuous variables to a rate of one =-=[18]-=-. Crucial to the acceptance of a new formal verification methodology by AMS designers is the ability to specify their circuits of interest using a familiar language. The previous approaches require th... |

11 | Formal verification of synthesized analog designs - Ghosh, Vemuri - 1999 |

10 | A formal approach to nonlinear analog circuit verification - Hedrich, Barke - 1995 |

9 | Semi-formal verification of VHDL-AMS descriptions - Salem - 2002 |

9 | Specification and compilation of timed systems
- Zheng
- 1998
(Show Context)
Citation Context ...s made when t fires. An example LHPN is shown in Fig. 3 which is automatically generated from the VHDL-AMS model in Fig. 2. The VHDL-AMS to LHPN compiler is built using a method similar to the one in =-=[22]-=-. The first two lines of the architecture in Fig. 2 set the initial values for Vout and c and sets the rate of change for c to 1. The second break statement is compiled into the LHPN shown in Fig. 3(a... |

4 | A symbolic core approach to the formal verification of integrated mixed-mode applications - Hendricx, Claesen - 1997 |

4 | The case for analog circuit verification
- Myers, Harrison, et al.
(Show Context)
Citation Context ...e to noise and uncertainty in model parameters that the output slew rate has a variance of ±10 percent (i.e., ±(18 to 22) mV/µs). This circuit, therefore, must be verified for all values in the range =-=[20]-=-. Vin Φ1 Q1 C1 Vin = ±1V freq(Vin) = 5 kHz Φ2 Q2 − + C2 C1 = 1 pF C2 = 25 pF Vout freq(Φ1) = freq(Φ2) = 500 kHz dVout/dt = ±(18 to 22) mV/µs process begins by assigning inc18 to ’1’ (this uses the ass... |