## Division/Square-Root Using Comparison Multiples

### BibTeX

@MISC{Nikmehr_division/square-rootusing,

author = {Hooman Nikmehr},

title = {Division/Square-Root Using Comparison Multiples},

year = {}

}

### OpenURL

### Abstract

A new implementation for minimally redundant radix-4 floating-point SRT division/square-root (division/sqrt) with the recurrence in the signed-digit format is introduced. The implementation is developed based on the comparison multiples idea. In the proposed approach, the magnitude of the quotient (root) digit is calculated by comparing the truncated partial remainder with 2 limited precision multiples of the divisor (partial root). The digit sign is determined by investigating the polarity of the truncated partial remainder. A timing evaluation using the logical synthesis (Synopsys DC with Artisan 0.18 µm typical library) shows a latency of 2.5 ns for the recurrence of the proposed division/sqrt. This is less than of the conventional implementation.

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Citation Context ...d. In the recurrence (1), the dividend x and the divisor d are two normalised binary numbers in the range [0.5, 1). Also, q j+1 represents the quotient digit in the signed-digit (SD) redundant format =-=[12]-=- selected from the minimally redundant radix-4 digit set � � 2, 1, 0, 1, 2 , where m = −m. (2) In (1), the next partial remainder (PR) w[ j + 1] is represented in carrysave (CS) redundant format [12].... |

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Citation Context ...ons carried out using the method of logical effort [5] and the logic synthesis show considerable decrease in the execution time with respect to conventional implementations. 2 BACKGROUND Some surveys =-=[6, 2]-=- shows that most VLSI implementations of FP division are based on digit recurrence division algorithms known as SRT (SRT division algorithm was introduced independently by D. Sweeney [7], J. E. Robert... |

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Citation Context ...[ j]} 4 can be calculated by a 6-bit binary adder. 6 COMBINED DIVISION AND SQRT The IEEE 754 standard requires the designers to implement both division and sqrt in the FP units of the microprocessors =-=[11]-=-. Given the 8 B[j] w0 w1 w2 MSB 0 2 3 1 MSB MUX w[j] QDS* or RDS* On-the-Fly Conversion S 0 S 1 S 2 S 4w[j] MUX w 0 w 1 w 2 d or 1 -d or F1 -2d or F2 F 2d or 2 F PR Sign Det MUX MUX Reg. Mag(q j+1) or... |

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Citation Context |

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Citation Context ...comparisons, we develop the following alternative, which has more flexibility and results in a simpler implementation. A similar discussion on the comparison multiples method is given by Antelo et al =-=[16]-=- as: An alternative implementation is based on comparisons of the residual estimate with truncated multiples of the divisor, however, this implementation is rarely used in practice because it requires... |

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Citation Context ...ilation of the truncated redundant residual and comparison, so no advantage is obtained with respect to the implementation with selection constants. Despite these quotes, there are reports of radix-2 =-=[18]-=- and radix-8 [19] SRT division, based on the comparison multiples idea, that show relatively improved response time. Moreover, Jensen [20] reports that although a highly optimised divider implemented ... |

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Citation Context ...dix-4 FP SRT division. QDS ∗ refers to the QDS function without the PR sign detector. 3.8 Buffers Sice the comparators, the comparison sign detectors and the coder are on the FP divider critical path =-=[28]-=-, one way to decrease the recurrence critical path delay might be to minimise the fan out of the circuit supplying the QDS function’s comparators with {4w[ j]} 5 and {Mk} 5. So, as shown in Figure 4, ... |

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Citation Context ...teration. number of similarities between the recurrences of these two, it is very normal to implement a combined circuit that perform both operations. Examples of such implementations can be found in =-=[29, 30]-=-. Comparing the specification of FP SRT division and sqrt reveals that to match the recurrences, it is sufficient to modify the sqrt PR such that old w[ j] new w[ j] = . (36) 2 Having called new w[ j]... |

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Citation Context ... the signs are manipulated by a coder to obtain the correct value for q j+1. One recent implementation for the QDS function using comparators and selection constants is disclosed by Burgess and Hinds =-=[17]-=-. The QDS function is part of the divide/square root unit used in a vector processing chip called ARM VFPJ. As shown in Figure 3, to prevent carry propagation while comparing, w[ j] is represented in ... |

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(Show Context)
Citation Context ...constants. Despite these quotes, there are reports of radix-2 [18] and radix-8 [19] SRT division, based on the comparison multiples idea, that show relatively improved response time. Moreover, Jensen =-=[20]-=- reports that although a highly optimised divider implemented using the conventional approach is just slightly faster than its un-optimised counterpart implemented using the comparison multiples idea,... |

2 |
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(Show Context)
Citation Context ...he set {M1} 5 and {M2} 5, or the set ¬ {M1} 5 and ¬ {M2} 5, to the adders. The comparison results are two BSD numbers with up to 8 digits. However, investigation shows that no representation overflow =-=[21]-=- happens when calculating (12). Therefore, the results could be represented in 7 digits instead. This makes the size ofsc n X Y n n Carry Generator Sign(X-Y) Figure 5: An architecture for n-digit BSD ... |

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Citation Context ...teration. number of similarities between the recurrences of these two, it is very normal to implement a combined circuit that perform both operations. Examples of such implementations can be found in =-=[29, 30]-=-. Comparing the specification of FP SRT division and sqrt reveals that to match the recurrences, it is sufficient to modify the sqrt PR such that old w[ j] new w[ j] = . (36) 2 Having called new w[ j]... |

1 |
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(Show Context)
Citation Context ...es through the black components. After the well-published Pentium FDIV bug in 1994 [3], a considerable effort has been put to analysing the QDS function lookup table [13], studying its implementation =-=[14]-=- and verification [3, 15]. In addition, developing alternative approaches to implementing FP SRT division has been another agenda [10]. Recently, to implement the QDS function, a method using selectio... |

1 |
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(Show Context)
Citation Context ...uncated redundant residual and comparison, so no advantage is obtained with respect to the implementation with selection constants. Despite these quotes, there are reports of radix-2 [18] and radix-8 =-=[19]-=- SRT division, based on the comparison multiples idea, that show relatively improved response time. Moreover, Jensen [20] reports that although a highly optimised divider implemented using the convent... |

1 |
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(Show Context)
Citation Context ...ore efficient implementation for the sign detectors. Figure 5 represents an architecture for such sign detectors. The architecture is derived from the fundamental definition of the binary subtraction =-=[26]-=-. According to this definition, when performing n-bit subtraction Z = X − Y, the n-th carry sent out from the subtractor can be recognised as the inverse of the sign of Z. This sign is equal to the po... |