A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification

A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification (2003)

Cached

Download Links

[www-bsac.eecs.berkeley.edu]

by Boris Murmann , Student Member , Bernhard E. Boser

Venue:	IEEE J. Solid-State Circuits
Citations:	10 - 0 self

BibTeX

@ARTICLE{Murmann03a12-bit,
    author = {Boris Murmann and Student Member and Bernhard E. Boser},
    title = {A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification},
    journal = {IEEE J. Solid-State Circuits},
    year = {2003},
    volume = {38},
    pages = {328--329}
}

Bookmark

OpenURL

Abstract

Abstract—Precision amplifiers dominate the power dissipation in most high-speed pipelined analog-to-digital converters (ADCs). We propose a digital background calibration technique as an enabling element to replace precision amplifiers by simple powerefficient open-loop stages. In the multibit first stage of a 12-bit 75-MSamples/s proof-of-concept prototype, we achieve more than 60 % residue amplifier power savings over a conventional implementation. The ADC has been fabricated in a 0.35- m double-poly quadruple-metal CMOS technology and achieves typical differential and integral nonlinearity within 0.5 LSB and 0.9 LSB, respectively. At Nyquist input frequencies, the measured signal-to-noise ratio is 67 dB and the total harmonic distortion is 74 dB. The IC consumes 290 mW at 3 V and occupies 7.9 mmP. Index Terms—Analog-to-digital conversion, adaptive systems, calibration, CMOS analog integrated circuits, linearization techniques, parameter estimation. I.

Citations

38	Distortion Analysis of Analog Integrated Circuits - Wambacq, Sansen - 1998
31	A pipelined 5-Msample/s 9-bit analog-to-digital converter - Lewis, Gray - 1987
28	A 10 b, 20 Msample/s, 35 mW pipeline A/D converter - Cho, Gray - 1995
20	A 12 b 75 MS/s pipelined ADC using open-loop residue amplification - Murmann, Boser - 2003
18	A power optimized 13-b 5 Msamples/s pipelined analog-to-digital converter in 1.2-µm CMOS - Cline, Gray
17	Digital cancellation of D/A converter noise in pipelined A/D converters - Galton - 2000
16	Optimizing the Stage Resolution in Pipelined, Multistage, Analog-to-Digital Converters for Video Rate Applications - Lewis - 1992
13	A 13-b 10-Msample/s ADC digitally calibrated with oversampling Delta-Sigma converter - Shu, Song, et al. - 1995
6	A 2.5-V, 12-b, 5-MSample/s pipelined CMOS ADC - Yu, Lee - 1996
5	A 14-bit 10-MHz calibration-free CMOS pipelined A/D converter - Singer, Brooks - 1996
5	ÒAn 8b 80MSample/s pipelined ADC with background calibrationÓ - Ming, Lewis - 2000
5	Analog circuit performance and process scaling - Annema - 1999
5	A high-swing CMOS telescopic operational amplifier - Gulati, Lee - 1998
4	Systematic Design for Optimization of HighSpeed Self-Calibrated Pipelined A/D - Goes - 1998
4	Analog broadband communication circuits in pure digital deep sub-micron CMOS - Bult - 1999
3	et al., “A 15-b 1Msample/s digitally self-calibrated pipeline ADC,” JSSC - Karanicolas - 1993
2	A 69 mW 10 b 80 MS/s pipelined - Min, Kim, et al. - 2003
2	An 8-bit 13-MSamples/s digital-background-calibrated algorithmic ADC - Blecker, Erdo˘gan, et al. - 2000
2	et al., “A 20 GS/s 8 b ADC with a 1 MB memory in 0.18 "m CMOS - Poulton - 2003
2	Opris et al., “A Single-Ended 12-bit 20 MSample/s SelfCalibrating Pipeline A/D Converter - E - 1998
1	A 10 b 150 MS/s 123 mW 0.18 "m - Yoo - 2003
1	et al., “A 4 GS/s 8 b ADC in 0.35 "m CMOS - Poulton - 2002
1	A ROM compression method for continuous data - Yang, Kim - 2002