Simultaneous buffer and wire sizing for performance and power optimization

Simultaneous buffer and wire sizing for performance and power optimization (1996)

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by Jason Cong , Cheng-kok Koh , Kwok-shing Leung

Venue:	in Proc. Int. Symp. on Low Power Electronics and Design
Citations:	15 - 10 self

BibTeX

@INPROCEEDINGS{Cong96simultaneousbuffer,
    author = {Jason Cong and Cheng-kok Koh and Kwok-shing Leung},
    title = {Simultaneous buffer and wire sizing for performance and power optimization},
    booktitle = {in Proc. Int. Symp. on Low Power Electronics and Design},
    year = {1996},
    pages = {271--276}
}

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Citations

382	Circuits, interconnections and packaging for VLSI - Bakoglu - 1990
320	The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers - Elmore - 1948
170	Principles of CMOS VLSI Design – A systems Perspective, 2nd edition - Weste, Esraghian - 1993
91	Optimal wire sizing and buffer insertion for low power and a generalized delay model - Lillis, Cheng, et al. - 1995
71	Ginneken, “Buffer placement in distributed RC-Tree network for minimal Elmore delay - van - 1990
68	Provably good performance-driven global routing - Cong, Kahng, et al. - 1992
62	Performance-Driven Interconnect Design Based on Distributed RC Delay Model - Cong, Leung, et al. - 1993
49	Simultaneous driver and wire sizing for performance and power optimization - Cong, Koh - 1994
45	Zero-skew clock routing trees with minimum wirelength - Boese, Kahng - 1992
43	Zero skew clock net routing - Chao, Hsu, et al. - 1992
41	RC interconnect optimization under the Elmore delay model - Sapatnekar - 1994
38	High-Performance Routing Trees with Identified Critical Sinks - Boese, Kahng, et al. - 1993
38	Optimal wiresizing for interconnects with multiple sources - Cong, He - 1996
27	Ginneken, "Buffer placement in distributed RC-tree networks for minimal Elmore delay - van - 1990
26	Optimal Wiresizing under Elmore Delay Model - Cong, Leung - 1995
26	A Direct Combination of the Prim and Dijkstra Constructions for Improved Performance-Driven Global Routing - Alpert - 1992
26	Performance-Driven Steiner Tree Algorithms for Global Routing - Hong, Xue, et al. - 1993
24	Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation - Chen, Chang, et al. - 1996
24	Critical Net Routing - Cohoon, Randall - 1991
17	Minimum-cost bounded-skew clock routing - Cong, Koh - 1995
17	Minimum skew and minimum path length routing - Edahiro - 1991
14	Bounded-skew clock and steiner routing under elmore delay - Cong, Kahng, et al. - 1995
11	Switch-Level Delay Models for Digital MOS VLSI - Ousterhout - 1984
10	Power optimal buffered clock tree design - Vittal, Marek-Sadowska - 1995
7	On the Bounded-SkewRouting Tree - Huang, Kahng, et al. - 1995
6	On the bounded-skew routing tree problem - HUANG, KAHNG, et al. - 1995
5	Wiresizing with Driver Sizing for Performance and Power Optimization - Cong, Koh, et al. - 1994
5	Simultaneous Buffer and Wire Sizing for Performance and - Cong, Koh, et al. - 1996
4	SimultaneousDriver and Wire Sizing for Performanceand Power Optimization - Cong, Koh - 1994
3	Simultaneous Driver and Wire Sizing for Performanceand Power Optimization - Cong, Koh - 1994
1	Simultaneous Gate and InterconnectSizing for Circuit-Level Delay Optimization - Menezes, Pullela, et al. - 1995
1	High-PerformanceRoutingTrees With Identified Critical Sinks - Boese, Kahng, et al. - 1993
1	The TransientResponseof DampedLinearNetwork with Particular Regard to WidebandAmplifier - Elmore
1	Pillage, “SimultaneousGate and InterconnectSizing for Circuit-Level Delay Optimization - Menezes, Pullela, et al. - 1995