## Simultaneous buffer and wire sizing for performance and power optimization (1996)

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Venue: | in Proc. Int. Symp. on Low Power Electronics and Design |

Citations: | 19 - 10 self |

### BibTeX

@INPROCEEDINGS{Cong96simultaneousbuffer,

author = {Jason Cong and Cheng-kok Koh and Kwok-shing Leung},

title = {Simultaneous buffer and wire sizing for performance and power optimization},

booktitle = {in Proc. Int. Symp. on Low Power Electronics and Design},

year = {1996},

pages = {271--276}

}

### OpenURL

### Abstract

### Citations

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Circuits, Interconnections, and Packaging for VLSI
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Citation Context ...ot difficult to see that this method is overly restrictive in that it did not consider buffers in the interconnect tree which are normally inserted to distribute the capacitive load among the buffers =-=[2]-=-. The works by [25, 21, 26] consider buffer insertion for either performance optimization or power minimization. In this paper, we propose to solve the problem of simultaneous buffer and wire sizing (... |

396 | The transient response of damped linear networks - Elmore - 1948 |

212 |
Principles of CMOS VLSI design: a systems perspective
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Citation Context ... total capacitance CL driven by the driver, the capacitive dissipation of the single driver of size d is Power cap = f \Delta CL \Delta V 2 dd , where f is the switching frequency of the input signal =-=[15]-=-. To simplify the expression, we let L = f \Delta V 2 dd and write Power cap = L \Delta CL. Note that CL has three components: the diffusion capacitance of the driver, C d \Delta d, the wire capacitan... |

114 | Optimal wire sizing and buffer insertion for low power and a generalized delay model
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- 1995
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Citation Context ...nce trees [4], A-trees [8], and lowdelay trees [1] have been proposed to minimize interconnect delay. Interconnect delay can be further reduced by sizing device and wire. The wiresizing algorithms in =-=[8, 9, 5, 13, 11]-=- can minimize interconnect delay by optimally assigning different wire width to each wire segment in the interconnect design. Recently, [6, 12] explore the possibility of simultaneous driver/gate and ... |

89 |
Ginneken, “Buffer Placement in Distributed RC-tree Networks for Minimal Elmore Delay
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Citation Context ... wire width to each wire segment in the interconnect design. Recently, [6, 12] explore the possibility of simultaneous driver/gate and wire sizing for performance and power optimization. The works by =-=[14, 11]-=- consider buffer insertion for either performance optimization or power minimization. In this paper, we study the problem of simultaneous buffer and wire sizing (SBWS) for performance and power optimi... |

78 | Provably good performance-driven global routing
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- 1992
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Citation Context ...udies show that interconnect delay can be reduced by interconnect topology optimization for both general and clock nets. For example, interconnect topologies such as bounded-radius bounded-cost trees =-=[10]-=-, AHHK trees [1], maximum performance trees [8], A-trees [15], low-delay trees [4], and IDW/CFD trees [19] have been proposed to optimize general nets. For clock nets, zero-skew tree (ZST) constructio... |

69 | Performance-driven interconnect design based on distributed rc delay model
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- 1993
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Citation Context ... amount of power. Recent studies show that interconnect delay can be reduced by interconnect topology optimization. For example, interconnect topologies such as maximum performance trees [4], A-trees =-=[8]-=-, and lowdelay trees [1] have been proposed to minimize interconnect delay. Interconnect delay can be further reduced by sizing device and wire. The wiresizing algorithms in [8, 9, 5, 13, 11] can mini... |

55 | Zero-Skew Clock Routing Trees With Minimum Wirelength
- Boese, Kahng
- 1992
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Citation Context ...AHHK trees [1], maximum performance trees [8], A-trees [15], low-delay trees [4], and IDW/CFD trees [19] have been proposed to optimize general nets. For clock nets, zero-skew tree (ZST) construction =-=[3, 5, 17]-=- and bounded-skew tree (BST) construction [13, 20, 11] have been studied extensively. Interconnect delay can be further reduced by sizing device and wire. The wiresizing algorithms in [15, 16, 9, 24, ... |

53 |
Zero skew clock net routing
- Chao, Hsu, et al.
- 1992
(Show Context)
Citation Context ...AHHK trees [1], maximum performance trees [8], A-trees [15], low-delay trees [4], and IDW/CFD trees [19] have been proposed to optimize general nets. For clock nets, zero-skew tree (ZST) construction =-=[3, 5, 17]-=- and bounded-skew tree (BST) construction [13, 20, 11] have been studied extensively. Interconnect delay can be further reduced by sizing device and wire. The wiresizing algorithms in [15, 16, 9, 24, ... |

53 | Simultaneous driver and wire sizing for performance and power optimization
- Cong, Koh
- 1994
(Show Context)
Citation Context ...interconnect topology optimization and wiresizing optimization are effective when resistance ratio, i.e. the driver resistance versus unit wire resistance, is small in the design [15]. Very recently, =-=[14, 12]-=- explore the possibility of simultaneous driver and wire sizing (SDWS) for performance and power optimization. The follow-up work by [22] considers simultaneous gate and interconnect sizing to optimiz... |

50 | RC interconnect optimization under the Elmore delay model
- Sapatnekar
- 1994
(Show Context)
Citation Context ...nce trees [4], A-trees [8], and lowdelay trees [1] have been proposed to minimize interconnect delay. Interconnect delay can be further reduced by sizing device and wire. The wiresizing algorithms in =-=[8, 9, 5, 13, 11]-=- can minimize interconnect delay by optimally assigning different wire width to each wire segment in the interconnect design. Recently, [6, 12] explore the possibility of simultaneous driver/gate and ... |

42 | Optimal Wiresizing for Interconnects with Multiple Sources
- Cong, He
- 1995
(Show Context)
Citation Context ...nce trees [4], A-trees [8], and lowdelay trees [1] have been proposed to minimize interconnect delay. Interconnect delay can be further reduced by sizing device and wire. The wiresizing algorithms in =-=[8, 9, 5, 13, 11]-=- can minimize interconnect delay by optimally assigning different wire width to each wire segment in the interconnect design. Recently, [6, 12] explore the possibility of simultaneous driver/gate and ... |

38 | High-Performance Routing Trees with Identified Critical Sinks
- Boese, Kahng, et al.
- 1993
(Show Context)
Citation Context ... studies show that interconnect delay can be reduced by interconnect topology optimization. For example, interconnect topologies such as maximum performance trees [4], A-trees [8], and lowdelay trees =-=[1]-=- have been proposed to minimize interconnect delay. Interconnect delay can be further reduced by sizing device and wire. The wiresizing algorithms in [8, 9, 5, 13, 11] can minimize interconnect delay ... |

29 |
Fast Performance-Driven Optimization for Buffered Clock Trees Based
- Chen, Chang, et al.
- 1996
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Citation Context ...Although there is a polynomial time algorithm for minimizing maximum delay [11], the actual run-time is long and the memory requirement is prohibitively large (see experimental results in Section 5). =-=[2]-=- shows that by assigning appropriate weight of each sink basedon Lagrangianrelaxation, the weighted-sum formulation can be used iteratively to minimize maximum delay. Therefore, coupled with Lagrangia... |

28 |
Optimal wiresizing under Elmore delay model
- Cong, Leung
- 1995
(Show Context)
Citation Context |

27 |
Ginneken, "Buffer placement in distributed RC-tree networks for minimal Elmore delay
- van
- 1990
(Show Context)
Citation Context ... wire width to each wire segment in the interconnect design. Recently, [6, 12] explore the possibility of simultaneous driver/gate and wire sizing for performance and power optimization. The works by =-=[14, 11]-=- consider buffer insertion for either performance optimization or power minimization. In this paper, we study the problem of simultaneous buffer and wire sizing (SBWS) for performance and power optimi... |

27 |
A Performance-Driven Steiner Tree Algorithm Us lobal Ro 6(3
- Hong
(Show Context)
Citation Context ...nd clock nets. For example, interconnect topologies such as bounded-radius bounded-cost trees [10], AHHK trees [1], maximum performance trees [8], A-trees [15], low-delay trees [4], and IDW/CFD trees =-=[19]-=- have been proposed to optimize general nets. For clock nets, zero-skew tree (ZST) construction [3, 5, 17] and bounded-skew tree (BST) construction [13, 20, 11] have been studied extensively. Intercon... |

24 | A Direct Combination of the Prim and Dijkstra Constructions for Improved Performance-Driven Global Routing
- Alpert
- 1992
(Show Context)
Citation Context ...nterconnect delay can be reduced by interconnect topology optimization for both general and clock nets. For example, interconnect topologies such as bounded-radius bounded-cost trees [10], AHHK trees =-=[1]-=-, maximum performance trees [8], A-trees [15], low-delay trees [4], and IDW/CFD trees [19] have been proposed to optimize general nets. For clock nets, zero-skew tree (ZST) construction [3, 5, 17] and... |

23 |
Critical Net Routing
- Cohoon, Randall
- 1991
(Show Context)
Citation Context ...a significant amount of power. Recent studies show that interconnect delay can be reduced by interconnect topology optimization. For example, interconnect topologies such as maximum performance trees =-=[4]-=-, A-trees [8], and lowdelay trees [1] have been proposed to minimize interconnect delay. Interconnect delay can be further reduced by sizing device and wire. The wiresizing algorithms in [8, 9, 5, 13,... |

20 | Minimum-cost bounded-skew clock routing”, Proc
- Cong, Koh
- 1995
(Show Context)
Citation Context ...nd-conquer approach towards solving this very difficult problem. Together with the results on bounded-skew tree routing where the clock tree has a maximum skew no larger than the specified skew bound =-=[13, 20, 11]-=-, the results presented in this paper and [12] will be the enabling tools for the aforementioned practical clock routing problem. Acknowledgements The authors would like to thank Dr. Charles Chien and... |

20 | Minimum skew and minimum path length routing in vlsi layout design - Edahiro - 1991 |

17 | Bounded-skew clock and steiner routing under elmore delay
- Cong, Kahng, et al.
- 1995
(Show Context)
Citation Context ...es [15], low-delay trees [4], and IDW/CFD trees [19] have been proposed to optimize general nets. For clock nets, zero-skew tree (ZST) construction [3, 5, 17] and bounded-skew tree (BST) construction =-=[13, 20, 11]-=- have been studied extensively. Interconnect delay can be further reduced by sizing device and wire. The wiresizing algorithms in [15, 16, 9, 24, 21] can minimize interconnect delay by optimally assig... |

13 |
Power optimal buffered clock tree design
- Vittal, Marek-Sadowska
- 1996
(Show Context)
Citation Context ...e that this method is overly restrictive in that it did not consider buffers in the interconnect tree which are normally inserted to distribute the capacitive load among the buffers [2]. The works by =-=[25, 21, 26]-=- consider buffer insertion for either performance optimization or power minimization. In this paper, we propose to solve the problem of simultaneous buffer and wire sizing (SBWS) for performance and p... |

12 | Switch-Level Delay Models for Digital MOS VLSI - Ousterhout - 1984 |

7 | High-Performance Routing Trees - Boese, Kahng, et al. - 1993 |

6 |
On the bounded-skew routing tree problem
- HUANG, KAHNG, et al.
- 1995
(Show Context)
Citation Context ...es [15], low-delay trees [4], and IDW/CFD trees [19] have been proposed to optimize general nets. For clock nets, zero-skew tree (ZST) construction [3, 5, 17] and bounded-skew tree (BST) construction =-=[13, 20, 11]-=- have been studied extensively. Interconnect delay can be further reduced by sizing device and wire. The wiresizing algorithms in [15, 16, 9, 24, 21] can minimize interconnect delay by optimally assig... |

5 | Wiresizing with Driver Sizing for Performance and Power Optimization
- Cong, Koh, et al.
- 1994
(Show Context)
Citation Context ...interconnect topology optimization and wiresizing optimization are effective when resistance ratio, i.e. the driver resistance versus unit wire resistance, is small in the design [15]. Very recently, =-=[14, 12]-=- explore the possibility of simultaneous driver and wire sizing (SDWS) for performance and power optimization. The follow-up work by [22] considers simultaneous gate and interconnect sizing to optimiz... |

5 |
Simultaneous Buffer and Wire Sizing for Performance and
- Cong, Koh, et al.
- 1996
(Show Context)
Citation Context ...f the buffered tree T as follows: tT�D�W � � ∑ λDi all Di �tTi�D�W � (3) where tTi is the performance measure of the unbuffered tree Ti driven by buffer Di. The details of the derivation are given in =-=[7]-=-. We can conclude from the above equation that if we are given the buffer sizes, we can obtain an optimal wiresizing solution by applying the technique in [9]. 2.2 Trade-Off Between Performance and Po... |

4 |
SimultaneousDriver and Wire Sizing for Performance and
- Cong, Koh
- 1994
(Show Context)
Citation Context ... device and wire. The wiresizing algorithms in [8, 9, 5, 13, 11] can minimize interconnect delay by optimally assigning different wire width to each wire segment in the interconnect design. Recently, =-=[6, 12]-=- explore the possibility of simultaneous driver/gate and wire sizing for performance and power optimization. The works by [14, 11] consider buffer insertion for either performance optimization or powe... |

3 |
Simultaneous Driver and Wire Sizing for Performanceand Power Optimization
- Cong, Koh
- 1994
(Show Context)
Citation Context ... device and wire. The wiresizing algorithms in [8, 9, 5, 13, 11] can minimize interconnect delay by optimally assigning different wire width to each wire segment in the interconnect design. Recently, =-=[6, 12]-=- explore the possibility of simultaneous driver/gate and wire sizing for performance and power optimization. The works by [14, 11] consider buffer insertion for either performance optimization or powe... |

1 | Simultaneous Gate and InterconnectSizing for Circuit-Level Delay Optimization - Menezes, Pullela, et al. - 1995 |

1 |
High-PerformanceRoutingTrees With Identified Critical Sinks
- Boese, Kahng, et al.
- 1993
(Show Context)
Citation Context ...tion for both general and clock nets. For example, interconnect topologies such as bounded-radius bounded-cost trees [10], AHHK trees [1], maximum performance trees [8], A-trees [15], low-delay trees =-=[4]-=-, and IDW/CFD trees [19] have been proposed to optimize general nets. For clock nets, zero-skew tree (ZST) construction [3, 5, 17] and bounded-skew tree (BST) construction [13, 20, 11] have been studi... |

1 |
The TransientResponseof DampedLinearNetwork with Particular Regard to WidebandAmplifier
- Elmore
(Show Context)
Citation Context ... from the source driver D 1 to sink N i in the buffered tree T . Note that we use t T without superscript to denote the weighted sum of delay and t N T with superscript N i to denote the Elmore delay =-=[18]-=- from source driver to sink N i . The weighted-sum formulation can be used in two scenarios. For performance optimization, large l's are used for timing critical sinks. For clock skew minimization, cl... |

1 | Pillage, “SimultaneousGate and InterconnectSizing for Circuit-Level Delay Optimization - Menezes, Pullela, et al. - 1995 |