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A Reconfigurable Coprocessor for Finite Field Multiplication in GF(2 n)
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@MISC{_areconfigurable,
author = {},
title = {A Reconfigurable Coprocessor for Finite Field Multiplication in GF(2 n)},
year = {}
}
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Abstract
The performance of elliptic curve based public key cryptosystems is mainly appointed by the efficiency of the underlying finite field arithmetic. This work describes a reconfigurable finite field multiplier, which is implemented within the latest family of Field Programmable System Level Integrated Circuits FPSLIC from Atmel, Inc. The architecture of the coprocessor is adapted from Karatsuba’s divide and conquer algorithm and allows for a reasonable speedup of the top-level public key algorithms. The VHDL hardware models are automatically generated based on an eligible operand size, which permits the optimal utilization of a particular FPSLIC device. 1
Keyphrases
reconfigurable coprocessor finite field multiplication underlying finite field reasonable speedup elliptic curve vhdl hardware model conquer algorithm particular fpslic device eligible operand size karatsuba divide reconfigurable finite field multiplier top-level public key algorithm public key cryptosystems optimal utilization
