## Fast floorplanning by look-ahead enabled recursive bipartitioning (2005)

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Venue: | In Asia South Pacific Design Automation Conf |

Citations: | 22 - 2 self |

### BibTeX

@INPROCEEDINGS{Cong05fastfloorplanning,

author = {Jason Cong and Michail Romesis and Joseph R. Shinnerl},

title = {Fast floorplanning by look-ahead enabled recursive bipartitioning},

booktitle = {In Asia South Pacific Design Automation Conf},

year = {2005},

pages = {1119--1122}

}

### Years of Citing Articles

### OpenURL

### Abstract

A new paradigm is introduced for floorplanning any combination of fixed-shape and variable-shape blocks under tight fixed-outline area constraints and a wirelength objective. Dramatic improvement over traditional floorplanning methods is achieved by explicit construction of strictly legal layouts for every partition block at every level of a cutsize-driven, top-down hierarchy. By scalably incorporating legalization into the hierarchical flow, post-hoc legalization is successfully eliminated. For large floorplanning benchmarks, an implementation, called PATOMA, generates solutions with half the wirelength of state-of-the-art floorplanners in orders of magnitude less run time. Experiments on standard GSRC industry benchmarks compare an implementation, called PATOMA, to the Traffic floorplanner and to both the default and high-effort modes of the Parquet-2 floorplanner. With all blocks hard, PATOMA’s average wirelength is 38 % shorter than Traffic’s in the same run time. With all blocks soft, PATOMA on average produces wirelengths 16 % shorter than Parquet-2’s default mode and runs 37 ¢ faster. Compared to the high-effort mode of Parquet-2, PATOMA’s average wirelength is 8 % shorter, and it runs 824 ¢ faster, on average. I.

### Citations

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Citation Context ... however, it handles both soft and hard blocks under a fixed-outline constraint. Both ZDS and ROB perform well in reasonable run time. They are reviewed in Sections IV and V below. PATOMA uses hMetis =-=[22]-=-, the well-known cutsize-driven multilevel hypergraph partitioning package. Terminal propagation [14] is used to account for connections between partitions. For a given user-specified area-imbalance t... |

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Citation Context ...ty; the results of these experiments were not tabulated. C. Hard and Soft Blocks Together In the fourth set of experiments, we generated large-scale floorplanning benchmarks from the IBM/ISPD98 suite =-=[6]-=- that include both hard and soft blocks on a fixed die with 20% whitespace. The soft blocks are clusters of standard cells generated by the First Choice clustering heuristic [22]. The hard blocks are ... |

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Citation Context ... representation of geometric relationships among modules. They can be divided into two major categories: slicing and general algorithms. The first slicing algorithms were developed in the 1980s [28], =-=[39]-=-. In the 1990s, general algorithms that do not require slicing cuts became more popular, especially after the introduction of the bounded slicing grids (BSG) [27] and sequence pair [26] representation... |

102 |
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Citation Context ...form well in reasonable run time. They are reviewed in Sections IV and V below. PATOMA uses hMetis [22], the well-known cutsize-driven multilevel hypergraph partitioning package. Terminal propagation =-=[14]-=- is used to account for connections between partitions. For a given user-specified area-imbalance tolerance t, hMetis attempts to find a partition V = V1 ∪ V2 of the vertex set V subject to the constr... |

98 | B*-Trees: A new representation for non-slicing floorplans
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Citation Context ...lly after the introduction of the bounded slicing grids (BSG) [27] and sequence pair [26] representations. Other nonslicing representations include transitive closure graphbased (TCG) [25], B ∗ -tree =-=[12]-=-, corner block list (CBL) [17], O-tree [15], [29], and so on. With the exception of the O-tree-based work [15], [29], simulated annealing (SA) has been used to minimize the area and/or the wirelength ... |

83 | Dragon2000: Standard-cell placement tool for large industry circuits
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Citation Context ...lution quality on fixed-outline problems. Fast recursive cutsize-driven area bisection by multilevel netlist partitioning is very successfully and widely used in large-scale placement [7], [8], [23], =-=[37]-=-. To date, however, the quality of bisection-based floorplanners has generally fallen short of that of the best SAbased implementations. We believe that this deficiency has been caused largely by a th... |

79 | Implementation and Extensibility of an Analytic Placer
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Citation Context ...LSI circuits, for two reasons. First, system designers require a means of rapidly estimating the variation in performance of alternative architectures and logic designs. Second, multiscale [8], [24], =-=[15]-=- and mixed-size [26], [2], [17] placement algorithms typically solve some form of floorplanning problem at the coarsest level of approximation, in order to generate an initial coarse placement for sub... |

73 | An O-Tree Representation of NonSlicing Floorplan and Its Applications
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Citation Context ...licing grids (BSG) [27] and sequence pair [26] representations. Other nonslicing representations include transitive closure graphbased (TCG) [25], B ∗ -tree [12], corner block list (CBL) [17], O-tree =-=[15]-=-, [29], and so on. With the exception of the O-tree-based work [15], [29], simulated annealing (SA) has been used to minimize the area and/or the wirelength under each of these representations. The fl... |

70 |
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Citation Context ...in the representation of geometric relationships among modules. They can be divided into two major categories: slicing and general algorithms. The first slicing algorithms were developed in the 1980s =-=[28]-=-, [39]. In the 1990s, general algorithms that do not require slicing cuts became more popular, especially after the introduction of the bounded slicing grids (BSG) [27] and sequence pair [26] represen... |

67 | Rectangle-packing-Based Module Placement
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Citation Context ...he 1980s [28], [39]. In the 1990s, general algorithms that do not require slicing cuts became more popular, especially after the introduction of the bounded slicing grids (BSG) [27] and sequence pair =-=[26]-=- representations. Other nonslicing representations include transitive closure graphbased (TCG) [25], B ∗ -tree [12], corner block list (CBL) [17], O-tree [15], [29], and so on. With the exception of t... |

64 | Multilevel generalized force-directed method for circuit placement
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- 2005
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Citation Context ...n (VLSI) circuits, for two reasons. First, system designers require a means of rapidly estimating the variation in performance of alternative architectures and logic designs. Second, multilevel [10], =-=[11]-=-, [21], [32] and mixed-size [3], [4], [20], [23], [34] placement algorithms typically solve some form of floorplanning problem at the coarsest level of approximation in order to generate an initial co... |

54 | Fixed-outline floorplanning through better local search
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- 2001
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Citation Context ...on in PATOMA. Section V describes the row-oriented block packing (ROB) heuristic for floorplanning a combination of hard and soft blocks. Section VI compares PATOMA’s performance with that of Parquet =-=[1]-=- and other nonannealing-based floorplanners. The paper is concluded in Section VII. II. OVERVIEW OF PATOMA ALGORITHM PATOMA attempts to minimize the total wirelength under a fixed-outline area constra... |

49 | Consistent Placement of Macro-Blocks using Floorplanning and Standard-Cell
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Citation Context ...ns. First, system designers require a means of rapidly estimating the variation in performance of alternative architectures and logic designs. Second, multilevel [10], [11], [21], [32] and mixed-size =-=[3]-=-, [4], [20], [23], [34] placement algorithms typically solve some form of floorplanning problem at the coarsest level of approximation in order to generate an initial coarse placement for subsequent i... |

44 | TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans”, DAC
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(Show Context)
Citation Context ...popular, especially after the introduction of the bounded slicing grids (BSG) [27] and sequence pair [26] representations. Other nonslicing representations include transitive closure graphbased (TCG) =-=[25]-=-, B ∗ -tree [12], corner block list (CBL) [17], O-tree [15], [29], and so on. With the exception of the O-tree-based work [15], [29], simulated annealing (SA) has been used to minimize the area and/or... |

41 | Classical Floorplanning Harmful
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(Show Context)
Citation Context ...s not support a fixed-outline constraint, and its run time is O(n 2 ) in the number of blocks. The precise purpose and the best formulation of floorplanning are subject to some debate. In 2000, Kahng =-=[18]-=- cited five key problems with conventional approaches: 1) packing-driven rather than connectivity-driven algorithms and benchmarks; 2) an unnecessary restriction to rectangular shapes, including “L” o... |

32 |
Min-cut Placement
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- 1977
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Citation Context ...ame or better solution quality on fixed-outline problems. Fast recursive cutsize-driven area bisection by multilevel netlist partitioning is very successfully and widely used in large-scale placement =-=[7]-=-, [8], [23], [37]. To date, however, the quality of bisection-based floorplanners has generally fallen short of that of the best SAbased implementations. We believe that this deficiency has been cause... |

31 | Fractional cut: improved recursive bisection placement - Agnihotri, Yildiz, et al. - 2003 |

27 | Recursive bisection based mixed block placement
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- 2004
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Citation Context ...m designers require a means of rapidly estimating the variation in performance of alternative architectures and logic designs. Second, multilevel [10], [11], [21], [32] and mixed-size [3], [4], [20], =-=[23]-=-, [34] placement algorithms typically solve some form of floorplanning problem at the coarsest level of approximation in order to generate an initial coarse placement for subsequent iterative refineme... |

23 | An Analytic Placer for Mixed-size Placement and Timing-driven Placement
- Kahng, Wang
- 2004
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Citation Context ... system designers require a means of rapidly estimating the variation in performance of alternative architectures and logic designs. Second, multilevel [10], [11], [21], [32] and mixed-size [3], [4], =-=[20]-=-, [23], [34] placement algorithms typically solve some form of floorplanning problem at the coarsest level of approximation in order to generate an initial coarse placement for subsequent iterative re... |

21 | Global objectives for standard cell placement
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- 2001
(Show Context)
Citation Context ...one of the partitions. Various uses of multilevel partitioning and white space redistribution by cutline adjustment are already familiar in min-cut placers Capo [3], [4], [9] and Feng Shui [5], [23], =-=[40]-=-, [41]. Feedback to min-cut placement by relocation of ambiguous terminals has been considered by Kahng and Reda [19]. What distinguishes PATOMA’s use of feedback from these other forms is both its so... |

20 | Placement Feedback: A Concept and Method for Better Min-cut Placement, DAC 2004
- Kahng, Reda
(Show Context)
Citation Context ...re already familiar in min-cut placers Capo [3], [4], [9] and Feng Shui [5], [23], [40], [41]. Feedback to min-cut placement by relocation of ambiguous terminals has been considered by Kahng and Reda =-=[19]-=-. What distinguishes PATOMA’s use of feedback from these other forms is both its source—area-driven look-ahead floorplanners, and its result, the guaranteed legality of its final floorplan. III. ZDS A... |

19 |
Unification of partitioning, placement and floorplanning
- Adya, Chaturvedi, et al.
(Show Context)
Citation Context ...irst, system designers require a means of rapidly estimating the variation in performance of alternative architectures and logic designs. Second, multilevel [10], [11], [21], [32] and mixed-size [3], =-=[4]-=-, [20], [23], [34] placement algorithms typically solve some form of floorplanning problem at the coarsest level of approximation in order to generate an initial coarse placement for subsequent iterat... |

19 | Large-scale circuit placement
- Cong, Shinnerl, et al.
- 2005
(Show Context)
Citation Context ...gration (VLSI) circuits, for two reasons. First, system designers require a means of rapidly estimating the variation in performance of alternative architectures and logic designs. Second, multilevel =-=[10]-=-, [11], [21], [32] and mixed-size [3], [4], [20], [23], [34] placement algorithms typically solve some form of floorplanning problem at the coarsest level of approximation in order to generate an init... |

16 |
Floorplans, planar graphs, and layouts
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Citation Context ...er analyzed the theoretical upper bounds on the total area achieved by slicing floorplans of soft blocks [30], [42], or generate ZDS floorplans with no consideration of aspect-ratio constraints [36], =-=[38]-=-. The section also proves the properties of the algorithm. The ZDS algorithm used here is based on a recursive topdown area bipartitioning. At each step, the blocks in a region are separated into two ... |

15 |
Module packing based on the BSG-structure and IC layout applications
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- 1998
(Show Context)
Citation Context ...hms were developed in the 1980s [28], [39]. In the 1990s, general algorithms that do not require slicing cuts became more popular, especially after the introduction of the bounded slicing grids (BSG) =-=[27]-=- and sequence pair [26] representations. Other nonslicing representations include transitive closure graphbased (TCG) [25], B ∗ -tree [12], corner block list (CBL) [17], O-tree [15], [29], and so on. ... |

14 | An enhanced perturbing algorithm for floorplan desigh using the O-tree representation
- Pang, Cheng, et al.
- 2000
(Show Context)
Citation Context ... grids (BSG) [27] and sequence pair [26] representations. Other nonslicing representations include transitive closure graphbased (TCG) [25], B ∗ -tree [12], corner block list (CBL) [17], O-tree [15], =-=[29]-=-, and so on. With the exception of the O-tree-based work [15], [29], simulated annealing (SA) has been used to minimize the area and/or the wirelength under each of these representations. The floorpla... |

14 | How Good are Slicing Floorplans
- Young, Wong
- 1997
(Show Context)
Citation Context ... satisfy the constraints for most existing benchmarks. Previous work on this subject either analyzed the theoretical upper bounds on the total area achieved by slicing floorplans of soft blocks [30], =-=[42]-=-, or generate ZDS floorplans with no consideration of aspect-ratio constraints [36], [38]. The section also proves the properties of the algorithm. The ZDS algorithm used here is based on a recursive ... |

14 | Almost optimum placement legalization by minimum cost flow and dynamic programming
- Brenner, Pauli, et al.
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(Show Context)
Citation Context ...nement usually suffices to legalize, but in general some form of global legalization becomes essential to guarantee proper termination. Recently reported progress in the legalization of standard-cell =-=[5]-=- and mixed-size [17] placements depends on a significant amount of available white space (20% or more). When area constraints are tight, legalization usually increases wirelength significantly. The wo... |

12 | Slicing tree is a complete floorplan representation
- Lai, Wong
(Show Context)
Citation Context ...ss on the same circuit. In its current implementation, our method generates slicing floorplans only. The generality of slicing floorplans augmented by simple compaction has been shown by Lai and Wong =-=[24]-=-. The results presented here confirm that a good slicing algorithm can produce superior results, even without any compaction, particularly on relatively large floorplanning instances. It is possible t... |

9 | Sarrafzadeh: “Fast floorplanning for effective prediction and construction”, in
- Ranjan, Bazargan, et al.
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(Show Context)
Citation Context ...n 100 blocks at a time. Recently, however, growing numbers of IP blocks have increased the sizes of most floorplanning instances, prompting researchers to seek nonstochastic approaches. Ranjan et al. =-=[31]-=- propose a two-stage fast floorplanning algorithm. In the first stage, a hierarchy is generated by topdown recursive bipartitioning. Cutline orientations are selected from the bottom up in a way that ... |

9 |
Modern Placement Techniques
- Sarrafzadeh, Wang, et al.
- 2002
(Show Context)
Citation Context ...cuits, for two reasons. First, system designers require a means of rapidly estimating the variation in performance of alternative architectures and logic designs. Second, multilevel [10], [11], [21], =-=[32]-=- and mixed-size [3], [4], [20], [23], [34] placement algorithms typically solve some form of floorplanning problem at the coarsest level of approximation in order to generate an initial coarse placeme... |

8 | Chip-Planning, Placement and Global Routing of Macro/Custom Cell Integrated Circuits Using Simulated Annealing - Sechen - 1988 |

7 | An Area-Optimality Study of Floorplanning
- Cong, Nataneli, et al.
- 2004
(Show Context)
Citation Context ...or a given fixed-shape subregion and block subset. These algorithms must be fast and must usually find legal solutions if they exist. The first area-driven floorplanner ZDS is based on a recent study =-=[13]-=- of sufficient conditions for ZDS floorplanning of soft blocks. ZDS is used only when all the blocks in the subregion are soft. Otherwise, a second areadriven floorplanner based on ROB is used. ROB is... |

5 |
Improved cut sequences for partitioning-based placement
- Yildiz, Madden
- 2001
(Show Context)
Citation Context ... the partitions. Various uses of multilevel partitioning and white space redistribution by cutline adjustment are already familiar in min-cut placers Capo [3], [4], [9] and Feng Shui [5], [23], [40], =-=[41]-=-. Feedback to min-cut placement by relocation of ambiguous terminals has been considered by Kahng and Reda [19]. What distinguishes PATOMA’s use of feedback from these other forms is both its source—a... |

5 |
Modern Placement Techiques
- Sarrafzadeh, Wang, et al.
- 2002
(Show Context)
Citation Context ...n of VLSI circuits, for two reasons. First, system designers require a means of rapidly estimating the variation in performance of alternative architectures and logic designs. Second, multiscale [8], =-=[24]-=-, [15] and mixed-size [26], [2], [17] placement algorithms typically solve some form of floorplanning problem at the coarsest level of approximation, in order to generate an initial coarse placement f... |

4 |
floorplanning: Enabling hierarchical design
- “Fixed-outline
- 2003
(Show Context)
Citation Context ...s; 3) a lack of attention to scalability; 4) the inability to handle a fixed-outline constraint; 5) the lack of attention to the register-transfer level (RTL)-down methodology context. Recent efforts =-=[2]-=- to address some of these concerns have met with only partial success, highlighting in particular the difficulty of simultaneously considering 3) and 4). In this context, our paper can be viewed as a ... |

4 |
Improved algorithms for hypergraph partitioning
- Caldwell, Kahng, et al.
- 2000
(Show Context)
Citation Context ...r better solution quality on fixed-outline problems. Fast recursive cutsize-driven area bisection by multilevel netlist partitioning is very successfully and widely used in large-scale placement [7], =-=[8]-=-, [23], [37]. To date, however, the quality of bisection-based floorplanners has generally fallen short of that of the best SAbased implementations. We believe that this deficiency has been caused lar... |

4 | A novel geometric algorithm for fast wireoptimized floorplanning
- Sassone, Lim
(Show Context)
Citation Context ...than that obtained by an SA-based algorithm [39], with speed up of over 1000× in predictor mode (high speed) and 20× in constructor mode (high efsfort). More recently, a fast algorithm called Traffic =-=[33]-=- has been used to generate compact, low-wirelength floorplans without SA. Traffic also uses two stages. In the first stage, the blocks are divided into layers by linear multiway partitioning. In the s... |

4 |
Multilevel Circuit Placement, chapter 4 of Multilevel Optimization in VLSICAD
- Chan, Cong, et al.
- 2003
(Show Context)
Citation Context ...design of VLSI circuits, for two reasons. First, system designers require a means of rapidly estimating the variation in performance of alternative architectures and logic designs. Second, multiscale =-=[8]-=-, [24], [15] and mixed-size [26], [2], [17] placement algorithms typically solve some form of floorplanning problem at the coarsest level of approximation, in order to generate an initial coarse place... |

3 |
Corner block list representation and its application to floorplan optimization
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- 2004
(Show Context)
Citation Context ...the bounded slicing grids (BSG) [27] and sequence pair [26] representations. Other nonslicing representations include transitive closure graphbased (TCG) [25], B ∗ -tree [12], corner block list (CBL) =-=[17]-=-, O-tree [15], [29], and so on. With the exception of the O-tree-based work [15], [29], simulated annealing (SA) has been used to minimize the area and/or the wirelength under each of these representa... |

3 |
A non-slicing floorplanning algorithm using corner block list topological representation
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- 1999
(Show Context)
Citation Context ...require slicing cuts became more popular, especially after the introduction of the BSG [20] and Sequence Pair [19] representations. Other nonslicing representations include TCG [18], B*-tree [9], CBL =-=[13]-=-, O-tree [11], and so on. Simulated annealing (SA) has been used to minimize area and/or wirelength under each of these representations. Until a few years ago, the inherent slowness of SA was partiall... |

2 |
A tight upper bound for slicing floorplans
- Peixoto, Jacome, et al.
- 2000
(Show Context)
Citation Context ...ic and satisfy the constraints for most existing benchmarks. Previous work on this subject either analyzed the theoretical upper bounds on the total area achieved by slicing floorplans of soft blocks =-=[30]-=-, [42], or generate ZDS floorplans with no consideration of aspect-ratio constraints [36], [38]. The section also proves the properties of the algorithm. The ZDS algorithm used here is based on a recu... |

2 |
A class of zero wasted area floorplan for VLSI design
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(Show Context)
Citation Context ...t either analyzed the theoretical upper bounds on the total area achieved by slicing floorplans of soft blocks [30], [42], or generate ZDS floorplans with no consideration of aspect-ratio constraints =-=[36]-=-, [38]. The section also proves the properties of the algorithm. The ZDS algorithm used here is based on a recursive topdown area bipartitioning. At each step, the blocks in a region are separated int... |

2 | Global Routing of Macro/Custom Cell Integrated Circuits Using Simulated Annealing - Planning, Placement - 1988 |

2 | A theorem on partitioning a sorted list of numbers with an application to VLSI floorplanning
- Shinnerl
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(Show Context)
Citation Context ...block � � satisfies �©�¢s����� �¥� ¢ ��� � � � ��� � � ¢ where ��� � � � ����� denotes the aspect ratio of the smallest subregion in which � � is placed. Proof: Available online in a technical report =-=[27]-=-. The next lemma bounds the aspect ratio of sibling subregions in terms of their area ratio and the aspect ratio of their common parent subregion. Lemma 3.2: Suppose subregion � is partitioned into su... |

1 |
recursive bisection produce routable placements
- “Can
- 2000
(Show Context)
Citation Context ...a legal solution in at least one of the partitions. Various uses of multilevel partitioning and white space redistribution by cutline adjustment are already familiar in min-cut placers Capo [3], [4], =-=[9]-=- and Feng Shui [5], [23], [40], [41]. Feedback to min-cut placement by relocation of ambiguous terminals has been considered by Kahng and Reda [19]. What distinguishes PATOMA’s use of feedback from th... |