## The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays (2002)

### Cached

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### Other Repositories/Bibliography

by
M. S. Hrishikesh
,
Keith I. Farkas
,
Doug Burgert
,
Stephen W. Keckler
,
Premkishore Shivakumar

Venue: | in Proceedings of the 29th Annual International Symposium on Computer Architecture |

Citations: | 103 - 14 self |