Abstract

Abstract-Flash memory is becoming increasingly im-portant as nonvolatile storage for mobile consumer elec-tronics due to its low power consumption and shock resis-tance. However, it imposes technical challenges in that a write should be preceded by an erase operation, and that this erase operation can be performed only in a unit much larger than the write unit. To address these technical hur-dles, an intermediate software layer called a flash transla-tion layer (FTL) is generally employed to redirect logical ad-dresses from the host system to physical addresses in flash memory. Previous approaches have performed this address translation at the granularity of either a write unit (page) or an erase unit (block). In this paper, we propose a novel FTL design that combines the two different granularities in address translation. This is motivated by the idea that coarse grain address translation lowers resources required to maintain translation information, which is crucial in mo-bile consumer products for cost and power consumption reasons, while fine grain address translation is efficient in handling small size writes. Performance evaluation based on trace-driven simulation shows that the proposed scheme significantly outperforms previously proposed approaches. Index Terms-Flash memory, NAND-type flash memory, FTL, CompactFlash, address translation. I.

Citations