Abstract

Convolution is a fundamental operation in many signal and image processing applications. Since the computation and communication pattern in a conuolu-tzon operation is regular, a number of specaal archttec-tures have been designed and implemented for this op-erator. The Von Neumann architectures cannot meet the real-time requirements of applications that use con-volution as an intermediate step. We combine the advantages of systolic algorithms with the low cost of developing application specific designs using field pro-grammable gate arrays (FPGAs) to buald a scalable convolver for use in computer vision systems. The performance of the systolic algorithm of Kung et al. [I] as compared theoretically and experimentally with many other convolution algorithms reported in the lit-erature. The implementation of a convolution opera-tion on Splash 2, an attached processor based on Xilinx 4010 FPGAs, is reported with impressive performance gains. 1

Citations