A multi-bit sigma-delta ADC with an FIR DAC loop filter
by
Jeffrey Harrison
,
Neil Weste
BibTeX
@MISC{Harrison_amulti-bit,
author = {Jeffrey Harrison and Neil Weste},
title = {A multi-bit sigma-delta ADC with an FIR DAC loop filter},
year = {}
}
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Abstract
A new sigma-delta modulator architecture is described in which the loop filter is implemented in the DAC. An ADC with a four-bit quantiser, implemented in a 0.25 micron digital CMOS process, achieves 40dB SNR over a 60MHz signal bandwidth and consumes 220mW when clocked at 520MHz. The feedback architecture reduces track and hold performance requirements.
Citations
| 11 | An 8-bit 150-MHz CMOS A/D converter - Wang, Razavi - 2000 |
| 3 | Design of Multibit Noise-Shaping Data Converters - Kenney, Carley - 1993 |
| 2 | Nonlinear Sampled-Data Systems - Vidal - 1969 |
| 2 | Abidi, \A 10-b 100-MS/s CMOS A/D Converter - Kim, Kusayanagi, et al. - 1997 |
