## Timing optimization for multisource nets: characterization and optimal repeater insertion (1999)

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Venue: | IEEE TRANSATIONS ON COMPUTER AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS |

Citations: | 10 - 1 self |

### BibTeX

@INPROCEEDINGS{Lillis99timingoptimization,

author = {John Lillis and Chung-Kuan Cheng},

title = {Timing optimization for multisource nets: characterization and optimal repeater insertion},

booktitle = {IEEE TRANSATIONS ON COMPUTER AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS},

year = {1999},

pages = {322--331},

publisher = {}

}

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### Abstract

This paper presents new results in the area of timing optimization for multisource nets. The augmented RC-diameter (ARD) is suggested as a natural and practical performance measure and a linear time algorithm for computing the ARD of a multisource net is presented. Building on the ARD measure, we characterize the multisource optimization problem in terms of operations on piece-wise linear functions. This characterization is then used to develop an algorithm for optimal repeater insertion: for a given multisource topology the algorithm efficiently identifies an optimal assignment of repeaters to prescribed insertion points under the “min cost timing feasible” problem formulation. The algorithm has been implemented and computational results demonstrate the viability of the approach.

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Citation Context ...sed wire resistance at ever shrinking geometries, interconnect now plays an increasingly dominant role in overall performance. Techniques for interconnect optimization include buffer insertion (e.g., =-=[1]-=-, [9], [15], and [26]), performance driven topology synthesis (e.g., [2], [5], [11], [16], and [27]), wire sizing (e.g., [4], [15], and [22]) and various combinations of these techniques (e.g., [17], ... |

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Citation Context ...ented RC-Diameter (ARD) as a natural timing metric for multi-source optimization. (2) We demonstrate that the ARD can be computed in O(n) time and thus is no harder than computing an RC-radius (e.g., =-=[13]-=-). (3) We present an algorithm for a promising optimization technique in this area: optimal bi-directional repeater insertion. We adopt the objective of cost minimization This research was funded in p... |

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Citation Context ...t of a set of k-dimensional points S is the largest subset S 0 S such that, for all s1;s22 S 0 , s16 s2 and s26 s1. The problem of nding a minimal point set has a long history dating back at least to =-=[9]-=-. A variety of algorithms have been proposed; some achieve excellent asymptotic complexity (e.g. [9]) while others have been tuned for ease of implementation or fast expected run time (e.g., [1]). The... |

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Citation Context ...ave seen much research in automatic timing optimization for VLSI interconnect. Most of this work has focused on single-source interconnect optimization and includes buffer insertion (e.g., [16], [5], =-=[10]-=-), performance driven topology synthesis (e.g., [11]), and wire sizing (e.g., [2], [10], [14]). After considering the single-source case, it is natural to ask what can be done for multi-source nets si... |

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Citation Context ...at ever shrinking geometries, interconnect now plays an increasingly dominant role in overall performance. Techniques for interconnect optimization include buffer insertion (e.g., [1], [9], [15], and =-=[26]-=-), performance driven topology synthesis (e.g., [2], [5], [11], [16], and [27]), wire sizing (e.g., [4], [15], and [22]) and various combinations of these techniques (e.g., [17], and [20]). We note th... |

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Citation Context ...ncreasingly dominant role in overall performance. Techniques for interconnect optimization include buffer insertion (e.g., [1], [9], [15], and [26]), performance driven topology synthesis (e.g., [2], =-=[5]-=-, [11], [16], and [27]), wire sizing (e.g., [4], [15], and [22]) and various combinations of these techniques (e.g., [17], and [20]). We note that all of these cited works focus on optimizing single s... |

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Citation Context ...n to system objectives such as clock period. 2) We demonstrate that the ARD of a given topology can be computed in time and, thus, is no harder than computing an RC-radius (see, e.g., [18], [21], and =-=[25]-=-)—i.e., it is unnecessary to perform multiple singlesource computations. 3) Most significantly, we present an algorithm for optimal repeater (i.e., bidirectional buffer) insertion for a given routing ... |

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Citation Context ...], [15], and [26]), performance driven topology synthesis (e.g., [2], [5], [11], [16], and [27]), wire sizing (e.g., [4], [15], and [22]) and various combinations of these techniques (e.g., [17], and =-=[20]-=-). We note that all of these cited works focus on optimizing single source routing topologies. After considering the various single-source formulations, optimization techniques and algorithms, it is n... |

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Citation Context ...work has focused on single-source interconnect optimization and includes bu er insertion (e.g., [16], [5], [10]), performance driven topology synthesis (e.g., [11]), and wire sizing (e.g., [2], [10], =-=[14]-=-). After considering the single-source case, it is natural to ask what can be done for multi-source nets since buses are so prevalent in modern designs and are often a key determinant of system perfor... |

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Citation Context ...ask what can be done for multi-source nets since buses are so prevalent in modern designs and are often a key determinant of system performance. This topic has only recently received attention (e.g., =-=[4]-=-, [3], [15]) and is the topic of this paper. Our primary contributions are as follows. (1) We propose the Augmented RC-Diameter (ARD) as a natural timing metric for multi-source optimization. (2) We d... |

34 | Fidelity and nearoptimality of elmore-based routing constructions
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Citation Context ... an increasingly dominant role in overall performance. Techniques for interconnect optimization include buffer insertion (e.g., [1], [9], [15], and [26]), performance driven topology synthesis (e.g., =-=[2]-=-, [5], [11], [16], and [27]), wire sizing (e.g., [4], [15], and [22]) and various combinations of these techniques (e.g., [17], and [20]). We note that all of these cited works focus on optimizing sin... |

31 |
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Citation Context ...indirect relation to system objectives such as clock period. 2) We demonstrate that the ARD of a given topology can be computed in time and, thus, is no harder than computing an RC-radius (see, e.g., =-=[18]-=-, [21], and [25])—i.e., it is unnecessary to perform multiple singlesource computations. 3) Most significantly, we present an algorithm for optimal repeater (i.e., bidirectional buffer) insertion for ... |

28 |
Optimal wiresizing under Elmore delay model
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(Show Context)
Citation Context ...st of this work has focused on single-source interconnect optimization and includes bu er insertion (e.g., [16], [5], [10]), performance driven topology synthesis (e.g., [11]), and wire sizing (e.g., =-=[2]-=-, [10], [14]). After considering the single-source case, it is natural to ask what can be done for multi-source nets since buses are so prevalent in modern designs and are often a key determinant of s... |

27 |
Ginneken, "Buffer placement in distributed RC-tree networks for minimal Elmore delay
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(Show Context)
Citation Context ...ent years have seen much research in automatic timing optimization for VLSI interconnect. Most of this work has focused on single-source interconnect optimization and includes buffer insertion (e.g., =-=[16]-=-, [5], [10]), performance driven topology synthesis (e.g., [11]), and wire sizing (e.g., [2], [10], [14]). After considering the single-source case, it is natural to ask what can be done for multi-sou... |

27 |
PerformanceDriven Steiner Tree Algorithms For Global Routing
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Citation Context ...singly dominant role in overall performance. Techniques for interconnect optimization include buffer insertion (e.g., [1], [9], [15], and [26]), performance driven topology synthesis (e.g., [2], [5], =-=[11]-=-, [16], and [27]), wire sizing (e.g., [4], [15], and [22]) and various combinations of these techniques (e.g., [17], and [20]). We note that all of these cited works focus on optimizing single source ... |

26 |
Simultaneous Routing and Buffer Insertion for High Performance Interconnect
- Lillis, Cheng, et al.
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Citation Context ...., [1], [9], [15], and [26]), performance driven topology synthesis (e.g., [2], [5], [11], [16], and [27]), wire sizing (e.g., [4], [15], and [22]) and various combinations of these techniques (e.g., =-=[17]-=-, and [20]). We note that all of these cited works focus on optimizing single source routing topologies. After considering the various single-source formulations, optimization techniques and algorithm... |

19 | Interconnect Layout Optimization by Simultaneous Steiner Tree - Okamoto, Cong - 1996 |

18 |
Optimal wire sizing and buer insertion for low power and a generalized delay model
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Citation Context ...have seen much research in automatic timing optimization for VLSI interconnect. Most of this work has focused on single-source interconnect optimization and includes bu er insertion (e.g., [16], [5], =-=[10]-=-), performance driven topology synthesis (e.g., [11]), and wire sizing (e.g., [2], [10], [14]). After considering the single-source case, it is natural to ask what can be done for multi-source nets si... |

17 | More output-sensitive geometric algorithms (extended abstract
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Citation Context ... most multi-dimensional dynamic programming applications, a key issue in repeater insertion is the elimination of suboptimal solutions. Typically, a solution s is characterized by a set of k scalars s=-=[1]-=-;s[2]; :::; s[k]; assume w.l.o.g that minimization in each of these k dimensions is preferred. This induces a partial order on a set of solutions S; for s1;s22S,wehave the following s1 s2() s1[i] s2[i... |

13 |
Minimal delay interconnect design using alphabetic trees
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Citation Context ...role in overall performance. Techniques for interconnect optimization include buffer insertion (e.g., [1], [9], [15], and [26]), performance driven topology synthesis (e.g., [2], [5], [11], [16], and =-=[27]-=-), wire sizing (e.g., [4], [15], and [22]) and various combinations of these techniques (e.g., [17], and [20]). We note that all of these cited works focus on optimizing single source routing topologi... |

12 | Performance Driven Routing with Multiple Sources
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(Show Context)
Citation Context ...hat can be done for multi-source nets since buses are so prevalent in modern designs and are often a key determinant of system performance. This topic has only recently received attention (e.g., [4], =-=[3]-=-, [15]) and is the topic of this paper. Our primary contributions are as follows. (1) We propose the Augmented RC-Diameter (ARD) as a natural timing metric for multi-source optimization. (2) We demons... |

9 |
Buer Placement in Distributed RC-tree Networks for Minimum Elmore Delay
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Citation Context ...cent years have seen much research in automatic timing optimization for VLSI interconnect. Most of this work has focused on single-source interconnect optimization and includes bu er insertion (e.g., =-=[16]-=-, [5], [10]), performance driven topology synthesis (e.g., [11]), and wire sizing (e.g., [2], [10], [14]). After considering the single-source case, it is natural to ask what can be done for multi-sou... |

6 |
New Techniques for Performance Driven Routing with Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing
- Lillis, Cheng, et al.
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Citation Context ...tion for VLSI interconnect. Most of this work has focused on single-source interconnect optimization and includes bu er insertion (e.g., [16], [5], [10]), performance driven topology synthesis (e.g., =-=[11]-=-), and wire sizing (e.g., [2], [10], [14]). After considering the single-source case, it is natural to ask what can be done for multi-source nets since buses are so prevalent in modern designs and are... |

2 |
Delay Optimization Algorithms For Tree Models of MOS Circuits
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Citation Context ...ears have seen much research in automatic timing optimization for VLSI interconnect. Most of this work has focused on single-source interconnect optimization and includes bu er insertion (e.g., [16], =-=[5]-=-, [10]), performance driven topology synthesis (e.g., [11]), and wire sizing (e.g., [2], [10], [14]). After considering the single-source case, it is natural to ask what can be done for multi-source n... |

2 |
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Citation Context ... algorithms, it is natural to ask what can be done in the case of multisource nets since buses are so prevalent in modern designs. This topic has only recently received attention (e.g., [6], [7], and =-=[8]-=-, [24]) and is the topic of this paper. Our primary contributions in this area are as follows. 1) We adopt the augmented RC-diameter (ARD), a natural performance measure based on RC delay models, the ... |

1 |
Jeng et, al \Bidirectional Bus Repeater
- Huang, C
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Citation Context ...gle-source case. A primary issue is repeater design: should one use a pair of tri-state bu ers controlled by a bus arbiter 1 or more sophisticated \direction sensing" autonomous repeaters (e.g., =-=[8], [7]-=-)? Such decisions are largely dependent on designer preference [12] and are not addressed here. Fortunately, such issues appear to have little impact on the basic nature of the optimization problem an... |

1 |
New Design and Implementation for Signal Repeaters," VLSI/CAD workshop
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Citation Context ...e single-source case. A primary issue is repeater design: should one use a pair of tri-state bu ers controlled by a bus arbiter 1 or more sophisticated \direction sensing" autonomous repeaters (e=-=.g., [8]-=-, [7])? Such decisions are largely dependent on designer preference [12] and are not addressed here. Fortunately, such issues appear to have little impact on the basic nature of the optimization probl... |

1 |
Intel Corp., private communication
- Menezes
- 1996
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Citation Context ...nique extremely favorable. Further, it has been shown to be a feasible design technique in the high-end community and, in fact, is commonly used in the design of high-speed commercial microprocessors =-=[12]-=-. Nevertheless, some design and technology issues arise in to bi-directional repeater insertion which do not appear in the single-source case. A primary issue is repeater design: should one use a pair... |

1 |
Performance Driven Bus Bu er Insertion
- Tsai, Kao, et al.
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(Show Context)
Citation Context ...an be done for multi-source nets since buses are so prevalent in modern designs and are often a key determinant of system performance. This topic has only recently received attention (e.g., [4], [3], =-=[15]-=-) and is the topic of this paper. Our primary contributions are as follows. (1) We propose the Augmented RC-Diameter (ARD) as a natural timing metric for multi-source optimization. (2) We demonstrate ... |

1 |
Jeng et, al "Bidirectional Bus Repeater
- Huang, C
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(Show Context)
Citation Context ...le-source case. A primary issue is repeater design: should one use a pair of tri-state buffers controlled by a bus arbiter 1 or more sophisticated "direction sensing" autonomous repeaters (e=-=.g., [8], [7]-=-)? Such decisions are largely dependent on designer preference [12] and are not addressed here. Fortunately, such issues appear to have little impact on the basic nature of the optimization problem an... |

1 |
Performance Driven Bus Buffer Insertion
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(Show Context)
Citation Context ...an be done for multi-source nets since buses are so prevalent in modern designs and are often a key determinant of system performance. This topic has only recently received attention (e.g., [4], [3], =-=[15]-=-) and is the topic of this paper. Our primary contributions are as follows. (1) We propose the Augmented RC-Diameter (ARD) as a natural timing metric for multi-source optimization. (2) We demonstrate ... |

1 |
Intel Corp., personal communication
- Menezes
- 1996
(Show Context)
Citation Context ...al repeater insertion in part because it has achieved a certain degree of maturity in the high-end design community and in fact is commonly used in the design of high-speed commercial microprocessors =-=[19]-=-. However, it was also selected because it exercises many of the issues involved in multisource optimization and thus serves as a good testbed in which to illustrate these techniques. 2 We note that t... |

1 | Jeng et, al "Bidirectional Bus Repeater," United States Patent number 5,202,593 - Huang, C - 1993 |