## Formal Verification of the Pentium 4 Floating-Point Multiplier (2002)

Venue: | in Design, Automation and Test in Europe Conference and Exposition (DATE). IEEE |

Citations: | 5 - 0 self |

### BibTeX

@INPROCEEDINGS{Kaivola02formalverification,

author = {Roope Kaivola and Naren Narasimhan},

title = {Formal Verification of the Pentium 4 Floating-Point Multiplier},

booktitle = {in Design, Automation and Test in Europe Conference and Exposition (DATE). IEEE},

year = {2002},

pages = {20--27}

}

### OpenURL

### Abstract

We present the formal verification of the floating-point multiplier in the Intel IA-32 Pentium 4 microprocessor. The verification is based on a combination of theoremproving and BDD based model-checking tasks performed in a unified hardware verification environment. The tasks are tightly integrated to accomplish complete verification of the multiplier hardware coupled with the rounder logic. The approach does not rely on specialized representations like Binary Moment Diagrams or its variants.

### Citations

466 |
The Science of Programming
- Gries
- 1981
(Show Context)
Citation Context ...-postcondition framework was to enable reasoning about the flow of computation in a well-structured manner. The theory of pre-postcondition triples is a standard framework for specification (see e.g. =-=[8, 13]). In this approa-=-ch, statements about programs are triples ¡£¢¥¤£¦§¡£¨©¤ , where ¢ and ¨ are logical properties, and ¦ is a program. Such a triple formalizes the statement precondition ¢ guarantees po... |

232 | On the complexity of vlsi implementations and graph representations of boolean functions with application to integer multiplication
- Bryant
- 1991
(Show Context)
Citation Context ...bolic trajectory evaluation using binary decision diagrams (BDDs). Traditional state-based approaches and model-checking techniques based on BDDs do not perform well on multiplier circuits. Bryant in =-=[3]-=- proved that BDDs for multipliers grow exponentially in size regardless of the variable order. Several alternate solutions have been proposed but have met with limited success [4, 5, 6, 15, 20] Mechan... |

163 | The microarchitecture of the pentium 4 processor
- Sager, Group, et al.
- 2001
(Show Context)
Citation Context ...al product of the mantissa. The exponents of the input operands are added and based on the range of the full product, are adjusted appropriately by a separate logic. For more details, please refer to =-=[9]-=-. 4 Floating-Point Numbers and Rounding Our proof framework includes a general-purpose definition and theorem library for floating-point numbers and rounding. The library supports floating-point numbe... |

93 | Verification of Arithmetic Circuits with Binary Moment Diagrarns
- Bryant, Chen
- 1995
(Show Context)
Citation Context ... circuits. Bryant in [3] proved that BDDs for multipliers grow exponentially in size regardless of the variable order. Several alternate solutions have been proposed but have met with limited success =-=[4, 5, 6, 15, 20]-=- Mechanical theorem proving of multiplier circuits provides an alternative to automatic model checking. However, techniques based purely on reasoning have seen limited application due to the effort an... |

75 |
Signed Binary Multiplication Technique”, Quarterly
- Booth
- 1951
(Show Context)
Citation Context ...uct. The source mantissas are assumed to be bound by a function of some � constant which is known a priori. The booth encode function is a Radix- � � modification of the classic Booth encoding s=-=cheme [2]. It accepts a-=-n n-bit multiplier operand encoding bS1 by viewing S1 as a combination of � slices and invoking the Booth function recursively on every slice. � S1)¥ Booth(M, Booth (M-1, S1). . . ¦�� ��... |

55 | Hybrid decision diagrams overcoming the limitations of MTBDDs and BMDs
- CLARKE, FUJITA, et al.
- 1995
(Show Context)
Citation Context ... circuits. Bryant in [3] proved that BDDs for multipliers grow exponentially in size regardless of the variable order. Several alternate solutions have been proposed but have met with limited success =-=[4, 5, 6, 15, 20]-=- Mechanical theorem proving of multiplier circuits provides an alternative to automatic model checking. However, techniques based purely on reasoning have seen limited application due to the effort an... |

53 | Mechanical verification of concurrent systems with tla
- Engberg, Grønning, et al.
- 1992
(Show Context)
Citation Context ...ible to verify using either approach on its own. Kurshan and Lamport [16] did some verification of large multipliers constructed by simple recursive procedures using COSPAN and the TLP theorem prover =-=[7]. -=-Aagaard and Seger reported a verification effort on a small-scale 1 multiplier circuit [1] in the Voss [22] verification system. O’Leary et al. [17] verified IEEE compliance of floatingpoint hardwar... |

36 |
The formal verification of a pipelined double-precision IEEE floating-point multiplier
- Aagaard, Seger
- 1995
(Show Context)
Citation Context ...ion of large multipliers constructed by simple recursive procedures using COSPAN and the TLP theorem prover [7]. Aagaard and Seger reported a verification effort on a small-scale 1 multiplier circuit =-=[1] i-=-n the Voss [22] verification system. O’Leary et al. [17] verified IEEE compliance of floatingpoint hardware for the Pentium Pro processor using a combination of word-level model-checking and theorem... |

19 |
Word level symbolic model checking - a new approach for verifying arithmetic circuits
- Clarke, Zhao
- 1995
(Show Context)
Citation Context ... circuits. Bryant in [3] proved that BDDs for multipliers grow exponentially in size regardless of the variable order. Several alternate solutions have been proposed but have met with limited success =-=[4, 5, 6, 15, 20]-=- Mechanical theorem proving of multiplier circuits provides an alternative to automatic model checking. However, techniques based purely on reasoning have seen limited application due to the effort an... |

10 | Practical formal verification in microprocessor design
- Jones, O’Leary, et al.
(Show Context)
Citation Context ...d precision floating-point operation with IEEE rounding, flags and faults. The verification was carried out in the Forte verification environment - a combined model-checking and theoremproving system =-=[10]-=-. The interface language to Forte isFL, a lazy strongly-typed functional language in the ML family [18]. Model checking in Forte is done via symbolic trajectory evaluation (STE) [23]. Theorem proving ... |

8 |
Divider circuit verification with model checking and theorem proving. Pages 338–355
- Kaivola, Aagaard
- 2000
(Show Context)
Citation Context ... down to verifying the correctness of the booth encoding algorithm.sINIT � PPSPEC� � MULT (6) � � � � � � � � � ¦�� � ¢ � BoothsPPSPEC ¢s� �s� � 2For a gene=-=ral formulation of the inference rules, see [11] � ¥ ¦�� � �sFrom Formulas 4 and 6 and a pre-p-=-ost transfer inference rule, we get ¡ INIT ¤ � � ¥�������¥��§�¥¤�¤¦� �§�s¡ PPSPEC � MULT ¤ Based on Formulas 3 and 6, and using a pre-condition strengthen... |