Formal Verification of the Pentium 4 Floating-Point Multiplier (2002)
| Venue: | in Design, Automation and Test in Europe Conference and Exposition (DATE). IEEE |
| Citations: | 4 - 0 self |
BibTeX
@INPROCEEDINGS{Kaivola02formalverification,
author = {Roope Kaivola and Naren Narasimhan},
title = {Formal Verification of the Pentium 4 Floating-Point Multiplier},
booktitle = {in Design, Automation and Test in Europe Conference and Exposition (DATE). IEEE},
year = {2002},
pages = {20--27}
}
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Abstract
We present the formal verification of the floating-point multiplier in the Intel IA-32 Pentium 4 microprocessor. The verification is based on a combination of theoremproving and BDD based model-checking tasks performed in a unified hardware verification environment. The tasks are tightly integrated to accomplish complete verification of the multiplier hardware coupled with the rounder logic. The approach does not rely on specialized representations like Binary Moment Diagrams or its variants.
