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Towards optimal multi-level tiling for stencil computations (2007)
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| Venue: | 21st IEEE International Parallel and Distributed Processing Symposium (IPDPS |
| Citations: | 12 - 1 self |
BibTeX
@INPROCEEDINGS{Renganarayana07towardsoptimal,
author = {Lakshminarayanan Renganarayana and Manjukumar Harthikote-matha and Rinku Dewri and Sanjay Rajopadhye},
title = {Towards optimal multi-level tiling for stencil computations},
booktitle = {21st IEEE International Parallel and Distributed Processing Symposium (IPDPS},
year = {2007}
}
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Abstract
Stencil computations form the performance-critical core of many applications. Tiling and parallelization are two important optimizations to speed up stencil computations. Many tiling and parallelization strategies are applicable to a given stencil computation. The best strategy depends not only on the combination of the two techniques, but also on many parameters: tile and loop sizes in each dimension; computation-communication balance of the code; processor architecture; message startup costs; etc. The best choices can only be determined through design-space exploration, which is extremely tedious and error prone to do via exhaustive experimentation. We characterize the space of multi-level tilings and parallelizations for 2D/3D Gauss-Siedel stencil computation. A systematic exploration of a part of this space enabled us to derive a design which is up to a factor of two faster than the standard implementation. 1.
Keyphrases
stencil computation towards optimal multi-level tiling performance-critical core multi-level tiling important optimization design-space exploration standard implementation computation-communication balance systematic exploration many parameter message startup cost many tiling loop size gauss-siedel stencil computation error prone many application exhaustive experimentation parallelization strategy
