## Modeling the effect of technology trends on the soft error rate of combinational logic (2002)

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Citations: | 288 - 7 self |

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@INPROCEEDINGS{Shivakumar02modelingthe,

author = {Premkishore Shivakumar and Michael Kistler and Stephen W. Keckler and Doug Burger and Lorenzo Alvisi and Ibm Technical and Contacts John Keaty and Rob Bell and Ram Rajamony},

title = {Modeling the effect of technology trends on the soft error rate of combinational logic},

booktitle = {},

year = {2002},

pages = {389--398}

}

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### Abstract

This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to-end model that enables us to compute the soft error rates (SER) for existing and future microprocessor-style designs. The model captures the effects of two important masking phenomena, electrical masking and latchingwindow masking, which inhibit soft errors in combinational logic. We quantify the SER in combinational logic and latches for feature sizes from 600nm to 50nm and clock rates from 16 to 6 fan-out-of-4 delays. Our model predicts that the SER per chip of logic circuits will increase eight orders of magnitude by the year 2011 and at that point will be comparable to the SER per chip of unprotected memory elements. Our result emphasizes the need for computer system designers to address the risks of SER in logic circuits in future designs. 1

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Citation Context ...e placed between two latches in a single pipeline stage. The FO4 metric is technology independent and 1 FO4 roughly corresponds to 360 pico-seconds times the transistor’s drawn gate length in micron=-=s [12]-=-. In our model we use levelsensitive latches because their advantages in area and tolerance to clock load/skew make them attractive for superpipelined designs. 3 4 Methodology In most modern microproc... |

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Citation Context ... increase as device sizes decrease [15, 24, 25], though researchers differ on the rate of this increase. A method for estimating SER in CMOS SRAM circuits was recently developed by Hazucha & Svensson =-=[10]. -=-This model estimates SER due to atmospheric neutrons (neutrons with energies � 1MeV) for a range of submicron feature sizes. It is based on a verified empirical model for the 600nm technology, which... |

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Citation Context ... for constructing our chip model. The Alpha 21264 was designed for a 350nm process and has 15.2 million transistors on the die [18]. Based on a detailed area analysis of die photos of the Alpha 21264 =-=[17]-=-, we concluded that approximately 20% of transistors are in logic circuits and the remaining 80% are in storage elements in the form of latches, caches, branch predictors, and other memory structures.... |

50 |
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Citation Context ...e at each gate the slope decreases and hence the amplitude also decreases. We constructed a model for electrical masking by combining two existing models. We use the Horowitz rise and fall time model =-=[13]-=- to determine the rise and fall time of the output pulse, and the Logical Delay Degradation Effect Model [3] to determine the amplitude, and hence the duration, of the output pulse. Horowitz rise and ... |

46 |
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Citation Context ...p a large part, and in some cases a majority, of the chip area in modern microprocessors. Past research has shown that combinational logic is much less susceptible to soft errors than memory elements =-=[8, 19]-=-. Three phenomena provide combinational logic a form of natural resistance to soft errors: 1) logical masking, 2) electrical masking, and 3) latching-window masking. We develop models for electrical m... |

37 |
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Citation Context ...ased processor pipelining significantly increases the SER of logic circuits. Seifert et al. used experiments and simulation to determine the trend of soft error rate in the family of Alpha processors =-=[28]-=-. They conclude that the alpha particle susceptibility of both logic and memory circuits has decreased over the last few process generations. Our study shows an increasing susceptibility to neutron-in... |

29 |
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Citation Context ...ated work, and Section 8 concludes the paper. 2 Background 2.1 Particles that cause soft errors In the early 1980s, IBM conducted a series of experiments to measure the particle flux from cosmic rays =-=[32]-=-, the rate of flow expressed as the number of particles of a particular energy per square centimeter per second. For our work, the most important aspect of these results is that particles of lower ene... |

27 |
CMOS Technology Scaling and Its Impact on Cache Delay
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Citation Context ... [29]. Values for drawn gate length, supply voltage, and oxide thickness are taken directly from the roadmap. The remaining parameters were obtained using a scaling methodology developed by McFarland =-=[21]. We-=- adjusted McFarland’s formula for threshold voltage slightly to scale better to technologies with very low supply voltages, but all other parameters are based on McFarland’s model. 4.2 Charge to v... |

26 |
Critical charge calculations for a bipolar SRAM array
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Citation Context ...mum charge that is needed to flip the value stored in the cell, resulting in a soft error. The smallest charge that results in a soft error is called the critical charge ( ¢¡¤£¦¥¨§ ) of the S=-=RAM cell [7]. The rat-=-e at which soft errors occur is typically expressed in terms of Failures In Time (FIT), which measures the number of failures per ©���� hours of operation. A number of studies on soft errors ... |

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Citation Context ...umber of schemes have been proposed to detect or recover from transient errors in processor computations. All these techniques are either based on space redundancy (e.g. [1]) or time redundancy (e.g. =-=[22, 26, 27]-=-). We believe that techniques such as these combined with circuit and process innovations will be required to enable future construction of reliable high performance systems. Our work is significant b... |

23 |
Calculation of Soft Error Rate of Submicron CMOS Logic Circuits
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Citation Context ...and superpipelining on the soft error rate of combinational logic, previous experimental work has been done to estimate the soft error rate of storage and combinational logic in existing technologies =-=[25, 6, 16, 19, 24]-=-. Another method for estimating the neutron-induced SER uses the Modified Burst Generation Rate model [31]. This method uses nuclear theory to calculate the collected charge resulting from a particle ... |

22 |
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Citation Context ...p a large part, and in some cases a majority, of the chip area in modern microprocessors. Past research has shown that combinational logic is much less susceptible to soft errors than memory elements =-=[8, 19]-=-. Three phenomena provide combinational logic a form of natural resistance to soft errors: 1) logical masking, 2) electrical masking, and 3) latching-window masking. We develop models for electrical m... |

19 |
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Citation Context ...r theory to calculate the collected charge resulting from a particle strike. IBM developed the SEMM (Soft-Error Monte Carlo Modeling) program to determine whether chip designs meet SER specifications =-=[23]. The prog-=-ram calculates the SER of semiconductor chips due to ionizing radiation based on detailed layout, process information and circuit ( �¡¤£¦¥¨§ ) values. Some work has also been done to estimat... |

15 |
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Citation Context ...t originate from radioactive decay of impurities in chip and packaging materials. For circuits withs¢¡¤£¦¥¨§ in the range of 10-40 fC, the alpha particle SER becomes comparable to that of neut=-=ron SER [9]-=-. In our experiments, this range corresponds to SRAM cells and latches in 180nm and later technologies and logic circuits in 50nm and later technologies. Our model could be adapted to estimate the SER... |

11 |
In-Flight and Ground Testing of Single Event Upset Sensitivity in Static RAMs,” Accepted for publication
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Citation Context ...sures the number of failures per ©���� hours of operation. A number of studies on soft errors in SRAMs have concluded that the SER for constant area SRAM arrays will increase as device sizes =-=decrease [15, 24, 25]-=-, though researchers differ on the rate of this increase. A method for estimating SER in CMOS SRAM circuits was recently developed by Hazucha & Svensson [10]. This model estimates SER due to atmospher... |

9 |
Simple method for estimating neutron-induced soft error rates based on modified BGR model
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Citation Context ...he soft error rate of storage and combinational logic in existing technologies [25, 6, 16, 19, 24]. Another method for estimating the neutron-induced SER uses the Modified Burst Generation Rate model =-=[31]-=-. This method uses nuclear theory to calculate the collected charge resulting from a particle strike. IBM developed the SEMM (Soft-Error Monte Carlo Modeling) program to determine whether chip designs... |

8 |
Attenuation of Single Event Induced Pulses
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- 1997
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Citation Context ... clock rates. Baze et al. studied electrical masking in a chain of inverters and concluded that for pulses that successfully get latched electrical masking does not have any significant effect on SER =-=[2]-=-. They also allude to various parameters such as the chip model and the clock rate as factors that might affect the impact of this effect on the overall SER. Our results show that electrical masking d... |

7 |
2000 Logical modelling of delay degradation effect in static CMOS gates
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- 1984
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Citation Context ...cal masking by combining two existing models. We use the Horowitz rise and fall time model [13] to determine the rise and fall time of the output pulse, and the Logical Delay Degradation Effect Model =-=[3]-=- to determine the amplitude, and hence the duration, of the output pulse. Horowitz rise and fall time model: The Horowitz model calculates the rise and fall time of the output pulse based on the the i... |

7 |
Calculation of Cosmic-Ray Induced Soft Upsets and Scaling in VLSI Devices
- Petersen, Shapiro, et al.
- 1982
(Show Context)
Citation Context ...sures the number of failures per ©���� hours of operation. A number of studies on soft errors in SRAMs have concluded that the SER for constant area SRAM arrays will increase as device sizes =-=decrease [15, 24, 25]-=-, though researchers differ on the rate of this increase. A method for estimating SER in CMOS SRAM circuits was recently developed by Hazucha & Svensson [10]. This model estimates SER due to atmospher... |

5 |
A Logic-Level Model for -Particle Hits in CMOS Circuits
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Citation Context ...and superpipelining on the soft error rate of combinational logic, previous experimental work has been done to estimate the soft error rate of storage and combinational logic in existing technologies =-=[25, 6, 16, 19, 24]-=-. Another method for estimating the neutron-induced SER uses the Modified Burst Generation Rate model [31]. This method uses nuclear theory to calculate the collected charge resulting from a particle ... |

4 |
Effect of CMOS Miniaturization on Cosmic-RayInduced Error Rate
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(Show Context)
Citation Context ...sures the number of failures per ©���� hours of operation. A number of studies on soft errors in SRAMs have concluded that the SER for constant area SRAM arrays will increase as device sizes =-=decrease [15, 24, 25]-=-, though researchers differ on the rate of this increase. A method for estimating SER in CMOS SRAM circuits was recently developed by Hazucha & Svensson [10]. This model estimates SER due to atmospher... |

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- 2002
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Citation Context ...h of these component models and how they are combined to obtain an estimate for the SER of combinational logic. Additional details on our methodology can be found in an extended version of this paper =-=[30]-=-. 4.1 Device scaling model We constructed a set of Spice Level 3 technology models corresponding to the technology generations from the Semiconductor Industry Association (SIA) 1999 technology roadmap... |

3 |
Background Radiation and Soft Errors
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Citation Context ...sented ins� this paper). The valuess�� of the and parameters for 600nm, 350nm and 100nm are taken directly froms� [8]. � The and values scale approximately linearly with technology in a log-log scale =-=[7]-=-, so we determined the parameters for the remaining technologies from the curve obtained by fitting the existing points to a straight line in a log-log scale. The curve fitting was done using Matlab a... |

3 |
Transient Fault Detection via
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Citation Context ...ed by the high performance core. Since the recomputations have both a spatial and temporal gap they will not be affected by the temporal or spatial locality of the particles. Both AR-SMT [23] and SRT =-=[22]-=- rely on a hardware approach called “simultaneous multithreading”, in which a processor can execute multiple threads at the same time. The basic idea in both approaches is to execute instructions redu... |

2 |
Analysis of Single-Event Effects
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- 2000
(Show Context)
Citation Context ...o consider actual circuits and associated inputs. Massengill et al. developed a specialized VHDL simulator that could analyze soft faults in an actual circuit and model the effects of logical masking =-=[20]-=-. They found that effect of logical masking on SER depends heavily on circuit inputs. Effects similar to logical masking can also occur in memory elements. For example, if a soft error occurs in a mem... |