## Implementation and extensibility of an analytic placer (2004)

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Venue: | IEEE Trans. on CAD |

Citations: | 73 - 11 self |

### BibTeX

@INPROCEEDINGS{Kahng04implementationand,

author = {Andrew B. Kahng and Qinke Wang},

title = {Implementation and extensibility of an analytic placer},

booktitle = {IEEE Trans. on CAD},

year = {2004},

pages = {18--25}

}

### Years of Citing Articles

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### Citations

189 | GORDIAN: VLSI Placement by Quadratic Programming and Slicing Optimization
- Kleinhans, Sigl, et al.
- 1991
(Show Context)
Citation Context ...e [4] [32] has been successfully used. A number of placement tools fall into this category: recursive partition with min-cut objective [8] [23] [54] [60] (Capo, CPlace, FengShui), quadratic placement =-=[37]-=- [53] [56] (GORDIAN, PROUD), and analytic placement with linear wirelength [51] (GORDIAN-L). Recently, the Dragon [57] [58] placement tool was presented, combining annealing with recursive bisection. ... |

169 | Generic global placement and floorplanning
- Eisenmann, Johannes
- 1998
(Show Context)
Citation Context ...go, La Jolla, CA 92093-0114. E-mail: qiwang@cs.ucsd.edu. The current state-of-the-art placement tools can be classified into two categories, based on how they obtain a placement without cell overlaps =-=[15]-=-. The first class consists of algorithms that refine the existing placement to obtain a better overlapfree placement. For example, TimberWolf [52] is a well-known annealing based placement tool; it de... |

109 | Can recursive bisection alone produce routable placements
- Caldwell, Kahng, et al.
- 2000
(Show Context)
Citation Context ...cessary cell spreading. Within this approach, a min-cut objective [4], [32] has been successfully used. A number of placement tools fall into this category: recursive partition with min-cut objective =-=[8]-=-, [23], [54], [60], (Capo, CPlace, FengShui), quadratic placement [37], [53], [56] (GORDIAN, PROUD), and analytic placement with linear wirelength [51] (GORDIAN-L). Recently, the Dragon [57], [58] pla... |

103 |
Efficient and Effective Placement for Very Large Circuits
- Sun, Sechen
- 1995
(Show Context)
Citation Context ... on how they obtain a placement without cell overlaps [15]. The first class consists of algorithms that refine the existing placement to obtain a better overlapfree placement. For example, TimberWolf =-=[52]-=- is a well-known annealing based placement tool; it develops new placements by permuting an existing placement. The second class of algorithms uses top-down recursive partitioning to provide the neces... |

97 |
Linear complementarity, linear and nonlinear programming
- Murty
- 1988
(Show Context)
Citation Context ... is quite useful in finding an unconstrained minimum of a high-dimensional function f(x). A detailed treatment, along with a survey of descent-based methods for nonlinear programming, can be found in =-=[42]-=-. In general, the conjugate gradient method finds the minimum by executing a series of line minimizations (i.e., line searches). A line minimization corresponds to one-dimensional function minimizatio... |

80 | Multilevel circuit partitioning
- Alpert, Huang, et al.
- 1997
(Show Context)
Citation Context ...w placements by permuting an existing placement. The second class of algorithms uses top-down recursive partitioning to provide the necessary cell spreading. Within this approach, a min-cut objective =-=[4]-=-, [32] has been successfully used. A number of placement tools fall into this category: recursive partition with min-cut objective [8], [23], [54], [60], (Capo, CPlace, FengShui), quadratic placement ... |

77 | Analytical placement: A linear or a quadratic objective function
- Sigl, Doll, et al.
- 1991
(Show Context)
Citation Context ...is category: recursive partition with min-cut objective [8] [23] [54] [60] (Capo, CPlace, FengShui), quadratic placement [37] [53] [56] (GORDIAN, PROUD), and analytic placement with linear wirelength =-=[51]-=- (GORDIAN-L). Recently, the Dragon [57] [58] placement tool was presented, combining annealing with recursive bisection. Constructive methods based on (hybrids of) partitioning and analytical techniqu... |

77 | Timing-driven placement for FPGAs
- Marquardt, Betz, et al.
- 2000
(Show Context)
Citation Context ...ng method more attractive. There are two principles for assigning net weights. The main principle used in most algorithms is that a timing critical net should receive a heavy weight. For example, VPR =-=[41]-=- uses the following formula to assign weight to an edge : slack (13) Fig. 6. Placement after legalization of our placer for the ibm02 circuit. Linux/Pentium IV workstations. However, APlace is much sl... |

72 | Timing driven placement for large standard cell circuits
- Swartz, Sechen
- 1995
(Show Context)
Citation Context ...Previous Work Timing-driven placement has been studied extensively. Existing approaches can be broadly divided into two classes: path-based and net-based. A typical path-based approach [21] [28] [47] =-=[48]-=- usually considers all or a subset of paths directly within the problem formulation. The majority of this class of approaches are based on mathematical programming techniques. This class of algorithms... |

70 | Algorithms for Large-Scale Flat Placement
- Vygen
- 1997
(Show Context)
Citation Context ... has been successfully used. A number of placement tools fall into this category: recursive partition with min-cut objective [8] [23] [54] [60] (Capo, CPlace, FengShui), quadratic placement [37] [53] =-=[56]-=- (GORDIAN, PROUD), and analytic placement with linear wirelength [51] (GORDIAN-L). Recently, the Dragon [57] [58] placement tool was presented, combining annealing with recursive bisection. Constructi... |

65 |
Generation of performance constraints for layout
- Nair, Berman, et al.
- 1989
(Show Context)
Citation Context ...elay constraints is called delay budgeting. The main idea is to distribute slacks from the end-points of each path to constituent nets along the path, such that a zero-slack solution is obtained [12] =-=[43]-=-. A serious drawback of this class of algorithms is that delay budgeting is usually done in the circuit’s structural domain, without consideration of physical placement feasibility. As a result, it ma... |

65 | Multilevel hypergraph partitioning
- Karypis, Aggarwal, et al.
- 1997
(Show Context)
Citation Context ...cements by permuting an existing placement. The second class of algorithms uses top-down recursive partitioning to provide the necessary cell spreading. Within this approach, a min-cut objective [4], =-=[32]-=- has been successfully used. A number of placement tools fall into this category: recursive partition with min-cut objective [8], [23], [54], [60], (Capo, CPlace, FengShui), quadratic placement [37], ... |

61 | FastPlace: Efficient analytical placement using cell shifting, iterative local refinement and a hybrid net model
- Viswanathan, Chu
- 2005
(Show Context)
Citation Context ...culty of force and attractor-directed placement methods is that wirelength is easily damaged by improper forces and attractors. Recently, a fast placement algorithm with good quality was presented in =-=[55]-=-. Quadratic wirelength optimization and a cell shifting technique are iteratively applied to obtain a high-quality placement without cell overlapping. After quadratic optimization, a special cell shif... |

46 | Consistent Placement of Macro-Blocks using Floorplanning and Standard-Cell Placement
- Adya, Markov
- 2002
(Show Context)
Citation Context ...cer to handle mixed-size placement. Our extension is compared to recent academic tools: UCLA mPG-MS [11], Feng Shui (v2.4) [35] and a three stage placement-floorplanning-placement flow that uses Capo =-=[1]-=- [2]. For ten IBM-ISPD02 mixed-size circuits, the half-perimeter wirelength of our placer outperforms that of mPG-MS, Feng Shui and the Capo flow respectively by 24.7%, 4.0% and 26.0% on average. • We... |

44 |
Performance-Driven Placement of Cell Based IC’s
- Jackson, Kuh
- 1989
(Show Context)
Citation Context ...ement. A. Previous Work Timing-driven placement has been studied extensively. Existing approaches can be broadly divided into two classes: path-based and net-based. A typical path-based approach [21] =-=[28]-=- [47] [48] usually considers all or a subset of paths directly within the problem formulation. The majority of this class of approaches are based on mathematical programming techniques. This class of ... |

42 | Routability Driven White Space Allocation for Fixed-Die Standard-Cell Placement
- Yang, Choi, et al.
(Show Context)
Citation Context ...t objective [8] [23] [54] [60] (Capo, CPlace, FengShui), quadratic placement [37] [53] [56] (GORDIAN, PROUD), and analytic placement with linear wirelength [51] (GORDIAN-L). Recently, the Dragon [57] =-=[58]-=- placement tool was presented, combining annealing with recursive bisection. Constructive methods based on (hybrids of) partitioning and analytical techniques are usually fast and produce good results... |

38 |
A novel net weighting algorithm for timing-driven placement
- Kong
(Show Context)
Citation Context ... method developed to take pathsharing effects into consideration by computing the number of paths passing through each edge in the circuit. These numbers can then be used as net weights. Another work =-=[36]-=- proposed a solution that distinguishes timing-critical paths from noncritical paths, and scale the impact of all paths by their relative timing criticality. Given a weighting function D(slack, T ), t... |

38 |
PROUD: A Sea-Of-Gates Placement Algorithm
- Tsay, Kuh, et al.
- 1988
(Show Context)
Citation Context ... [32] has been successfully used. A number of placement tools fall into this category: recursive partition with min-cut objective [8] [23] [54] [60] (Capo, CPlace, FengShui), quadratic placement [37] =-=[53]-=- [56] (GORDIAN, PROUD), and analytic placement with linear wirelength [51] (GORDIAN-L). Recently, the Dragon [57] [58] placement tool was presented, combining annealing with recursive bisection. Const... |

34 |
An analytic net weighting approach for performance optimization in circuit placement
- Tsay, Koehl
- 1991
(Show Context)
Citation Context ... simultaneously minimized. For this reason, much of the recent timing-driven work [20] [45] [46] has been net-based. Unlike path-based approaches that handle paths directly, net-based approaches [15] =-=[49]-=- usually transform timing constraints or requirements into either net weight or net length (or delay) constraints, and employ a weighted wirelength minimization engine. The process of generating net-l... |

33 | Faster Minimization of Linear Wirelength for Global Placement
- Alpert, Chan, et al.
- 1998
(Show Context)
Citation Context ...iciently minimized. Convex nonlinear approximations of HPWL, which do not require net models and which permit direct inclusion of nonlinear delay terms, are proposed and well-studied in such works as =-=[3]-=- [6] [33] [34]. The approach of Naylor et al. [44] follows along similar lines, and uses a log-sumexp method to capture the linear half-perimeter wirelength while simultaneously obtaining the desirabl... |

33 |
Method and system for high speed detailed placement of cells within an integrated circuit design
- Hill
- 2002
(Show Context)
Citation Context ...ed by these figures, we set the iteration limit at 100 in our experiments below. D. Detailed Placement The placement results of APlace have cell overlaps and need to be legalized. A simplified Tetris =-=[22]-=- legalization algorithm is implemented in APlace; this algorithm also bears strong resemblance to the method proposed in a technical report of Li and Koh [40]. The Tetris legalization is applied after... |

31 | Multi-level placement for large-scale mixed-size IC designs
- Chang, Cong, et al.
- 2003
(Show Context)
Citation Context ...e QPlace (SE5.4), and 8.1% over UCLA Dragon (v3.01), and 14.1% over Capo (v8.7). • We extend the placer to handle mixed-size placement. Our extension is compared to recent academic tools: UCLA mPG-MS =-=[11]-=-, Feng Shui (v2.4) [35] and a three stage placement-floorplanning-placement flow that uses Capo [1] [2]. For ten IBM-ISPD02 mixed-size circuits, the half-perimeter wirelength of our placer outperforms... |

28 | Improved Cut Sequences for Partitioning Based Placement
- Yildiz, Madden
(Show Context)
Citation Context ...spreading. Within this approach, a min-cut objective [4] [32] has been successfully used. A number of placement tools fall into this category: recursive partition with min-cut objective [8] [23] [54] =-=[60]-=- (Capo, CPlace, FengShui), quadratic placement [37] [53] [56] (GORDIAN, PROUD), and analytic placement with linear wirelength [51] (GORDIAN-L). Recently, the Dragon [57] [58] placement tool was presen... |

27 | Recursive bisection based mixed block placement
- Khatkhate, Li, et al.
- 2004
(Show Context)
Citation Context ...1% over UCLA Dragon (v3.01), and 14.1% over Capo (v8.7). 4) We extend the placer to handle mixed-size placement. Our extension is compared to recent academic tools: UCLA mPG-MS [11], Feng Shui (v2.4) =-=[35]-=-, and a three-stage placement-floorplanning-placement flow that uses Capo [1], [2]. For ten IBM-ISPD02 mixed-size circuits, the HPWL of our placer outperforms that of mPG-MS, Feng Shui and the Capo fl... |

26 | Timing-driven placement based on partitioning with dynamic cut-net control
- Ou, Pedram
- 2000
(Show Context)
Citation Context ...timization, but its drawback is relatively high complexity due to the exponential number of paths that need to be simultaneously minimized. For this reason, much of the recent timing-driven work [20] =-=[45]-=- [46] has been net-based. Unlike path-based approaches that handle paths directly, net-based approaches [15] [49] usually transform timing constraints or requirements into either net weight or net len... |

26 | Timing-driven placement using design hierarchy guided constraint generation
- Yang
- 2002
(Show Context)
Citation Context ...analysis (STA). We use six industry circuits as our testcases. Two of them, mac1 and mac2, are among the ISPD 2001 Circuit Benchmarks [27] that first appeared in [13]. These circuits are also used in =-=[59]-=- as benchmarks for timing-driven placement. Only Verilog files are available for these two cases; they are synthesized with a commercial tool, Cadence BuildGates (v5.12). We use a 0.18µm standard-cell... |

23 | Timing driven placement using physical net constraints
- Halpin
- 2001
(Show Context)
Citation Context ...ng optimization, but its drawback is relatively high complexity due to the exponential number of paths that need to be simultaneously minimized. For this reason, much of the recent timing-driven work =-=[20]-=-, [45], [46] has been net-based. Unlike path-based approaches where is the current longest path delay, and is a constant called the criticality exponent. The other principle is path sharing: In genera... |

22 | An analytic placer for mixed-size placement and timingdriven placement - Kahng, Wang - 2004 |

21 |
Design Automation for Timing-Driven Layout Synthesis
- Sapatnekar, Kang
- 1993
(Show Context)
Citation Context ...erentiable and converges to HP W L(t) as α converges to 0. The log-sum-exp formula picks the most dominant terms; it has been previously used in physical design applications such as transistor sizing =-=[50]-=-. We minimize the wirelength objective function using the conjugate gradient optimizer. Initially, cells are randomly distributed over the placement area, and then the wirelength objective function in... |

20 |
Prime: a timing-driven placement tool using a piecewise linear resistive network approach
- Hamada, Cheng, et al.
- 1993
(Show Context)
Citation Context ... placement. A. Previous Work Timing-driven placement has been studied extensively. Existing approaches can be broadly divided into two classes: path-based and net-based. A typical path-based approach =-=[21]-=- [28] [47] [48] usually considers all or a subset of paths directly within the problem formulation. The majority of this class of approaches are based on mathematical programming techniques. This clas... |

19 | Potential Slack: An Effective Metric of Combinational Circuit Performance
- Chen, Yang, et al.
- 2000
(Show Context)
Citation Context ... netdelay constraints is called delay budgeting. The main idea is to distribute slacks from the end-points of each path to constituent nets along the path, such that a zero-slack solution is obtained =-=[12]-=- [43]. A serious drawback of this class of algorithms is that delay budgeting is usually done in the circuit’s structural domain, without consideration of physical placement feasibility. As a result, ... |

19 | Accurate pseudo-constructive wirelength and congestion estimation
- Kahng, Xu
- 2003
(Show Context)
Citation Context ...bility of placement results, we have integrated congestion information into the objective functions to direct cell distribution. We use Kahng and Xu’s accurate bend-based congestion estimation method =-=[31]-=- in our placer. If a particular grid is determined to be congested (resp. uncongested), the expected total cell potential of the grid in Equation (4) is reduced (resp. increased) accordingly. The sum ... |

17 |
Attractor-repeller approach for global placement
- Etawil, Arebi, et al.
- 1999
(Show Context)
Citation Context ...onal forces is proposed by [15]; in each iteration, a better spreading of cells is achieved without excessive net stretching. Another model of cell attracting and repelling (ARP) is presented in [16] =-=[17]-=-. Attractors (dummy cells) are added to sparse regions to drag cells from nearby dense regions, together with a cell repeller model that captures the wirelength objective. The ideas of additional forc... |

17 | FAR: Fixed-points addition and relaxation based placement
- Hu, Marek-Sadowska
- 2002
(Show Context)
Citation Context ... regions to drag cells from nearby dense regions, together with a cell repeller model that captures the wirelength objective. The ideas of additional forces and fixed pseudocells are also combined in =-=[24]-=-. The difficulty of force and attractor-directed placement methods is that wirelength is easily damaged by improper forces and attractors. Recently, a fast placement algorithm with good quality was pr... |

16 | Analytical minimization of halfperimeter wirelength
- Kennings, Markov
- 2000
(Show Context)
Citation Context ...mized. Convex nonlinear approximations of HPWL, which do not require net models and which permit direct inclusion of nonlinear delay terms, are proposed and well-studied in such works as [3] [6] [33] =-=[34]-=-. The approach of Naylor et al. [44] follows along similar lines, and uses a log-sumexp method to capture the linear half-perimeter wirelength while simultaneously obtaining the desirable characterist... |

16 |
et al., “Non-Linear Optimization System and Method for Wire Length and Delay Optimization for an Automatic Electric Circuit Placer
- Naylor
- 2001
(Show Context)
Citation Context ...th have recently received much attention from both academia and industry. A novel and simple objective function for spreading cells over the placement area is described in the patent of Naylor et al. =-=[44]-=-. When combined with a wirelength objective function, this allows efficient simultaneous cell spreading and wirelength optimization using nonlinear optimization techniques. In this work, we implement ... |

16 |
Linear decomposition algorithm for VLSI design applications
- Li, Lillis, et al.
- 1995
(Show Context)
Citation Context ...id nodes is larger than 60. B. Wirelength Formulation Minimization of wirelength is a common objective for circuit placement. Linear and quadratic wirelength objectives are typically used; see, e.g., =-=[39]-=- and [51] for comparisons. The where is a smoothing parameter. is strictly convex, continuously differentiable and converges to as converges to 0. The log-sum-exp formula picks the most dominant terms... |

15 |
Timing driven force directed placement with physical net constraints
- Rajagopal, Shaked, et al.
- 2003
(Show Context)
Citation Context ...ation, but its drawback is relatively high complexity due to the exponential number of paths that need to be simultaneously minimized. For this reason, much of the recent timing-driven work [20] [45] =-=[46]-=- has been net-based. Unlike path-based approaches that handle paths directly, net-based approaches [15] [49] usually transform timing constraints or requirements into either net weight or net length (... |

15 | Hypergraph partitioning for VLSI CAD: Methodology for heurisitc development, experimentation and reporting
- Caldwell, Kahng, et al.
- 1999
(Show Context)
Citation Context ...op-down hierarchical approach to accelerate APlace. During initialization, a hierarchy of clusters is constructed using MLPart 4.21, a leading-edge, open-source min-cut hypergraph/circuit partitioner =-=[7]-=-. The top-down hierarchical algorithm is described in Fig. 2. Notations used are summarized as follows. Cell. Number of cells. Maximum number of cluster levels. Number of clusters at level . Cluster o... |

14 |
Free Space Management for Cut-Based Placement
- Alpert, Nam, et al.
- 2002
(Show Context)
Citation Context ...oductivity increasingly requires the reuse of predesigned or generated macro blocks (processing and interface cores, embedded memories, etc.). This presents a “boulders and dust” challenge to placers =-=[5]-=-, where the sizes of placeable objects can vary by factors of 10,000 or more. In this section, we extend the APlace approach to address the mixed-size placement problem. Our focus is on two issues: (1... |

13 |
RITUAL: A Performance Driven Placement for Small-Cell ICs
- Srinivasan, Chaudhary, et al.
(Show Context)
Citation Context .... A. Previous Work Timing-driven placement has been studied extensively. Existing approaches can be broadly divided into two classes: path-based and net-based. A typical path-based approach [21] [28] =-=[47]-=- [48] usually considers all or a subset of paths directly within the problem formulation. The majority of this class of approaches are based on mathematical programming techniques. This class of algor... |

12 |
Partitioning-Based Standard Cell Global Placement with an Exact Objective
- Huang, Kahng
- 1997
(Show Context)
Citation Context ...sary cell spreading. Within this approach, a min-cut objective [4] [32] has been successfully used. A number of placement tools fall into this category: recursive partition with min-cut objective [8] =-=[23]-=- [54] [60] (Capo, CPlace, FengShui), quadratic placement [37] [53] [56] (GORDIAN, PROUD), and analytic placement with linear wirelength [51] (GORDIAN-L). Recently, the Dragon [57] [58] placement tool ... |

11 | A standard-cell placement tool for designs with high row utilization
- Yang
- 2002
(Show Context)
Citation Context ...in-cut objective [8] [23] [54] [60] (Capo, CPlace, FengShui), quadratic placement [37] [53] [56] (GORDIAN, PROUD), and analytic placement with linear wirelength [51] (GORDIAN-L). Recently, the Dragon =-=[57]-=- [58] placement tool was presented, combining annealing with recursive bisection. Constructive methods based on (hybrids of) partitioning and analytical techniques are usually fast and produce good re... |

8 |
Timing Driven Placement using
- Halpin, Chen, et al.
(Show Context)
Citation Context ...ng optimization, but its drawback is relatively high complexity due to the exponential number of paths that need to be simultaneously minimized. For this reason, much of the recent timing-driven work =-=[20]-=- [45] [46] has been net-based. Unlike path-based approaches that handle paths directly, net-based approaches [15] [49] usually transform timing constraints or requirements into either net weight or ne... |

8 |
On Improving Recursive BipartitioningBased Placement,” Purdue Univ
- Li, Koh
- 2003
(Show Context)
Citation Context ...need to be legalized. A simplified Tetris [22] legalization algorithm is implemented in APlace; this algorithm also bears strong resemblance to the method proposed in a technical report of Li and Koh =-=[40]-=-. The Tetris legalization is applied after global placement: cells are sorted according to their vertical coordinates, and then for each cell from left to right the current nearest available position ... |

8 |
On whitespace in mixed-size placement and physical sysnthesis
- Adya, Markov, et al.
(Show Context)
Citation Context ... handle mixed-size placement. Our extension is compared to recent academic tools: UCLA mPG-MS [11], Feng Shui (v2.4) [35], and a three-stage placement-floorplanning-placement flow that uses Capo [1], =-=[2]-=-. For ten IBM-ISPD02 mixed-size circuits, the HPWL of our placer outperforms that of mPG-MS, Feng Shui and the Capo flow respectively by 24.7%, 4.0%, and 26.0% on average. 5) We extend the placer to a... |

6 |
Smoothening Max-terms and Analytical
- Kennings, Markov
- 2002
(Show Context)
Citation Context ... minimized. Convex nonlinear approximations of HPWL, which do not require net models and which permit direct inclusion of nonlinear delay terms, are proposed and well-studied in such works as [3] [6] =-=[33]-=- [34]. The approach of Naylor et al. [44] follows along similar lines, and uses a log-sumexp method to capture the linear half-perimeter wirelength while simultaneously obtaining the desirable charact... |

6 | Markov Implications of Area-Array I/O for Row-Based Placement Methodology
- Caldwell, Kahng, et al.
- 1998
(Show Context)
Citation Context ...eventually dominate IC implementation methodology, affording improved pad count and reliability, and reduced noise coupling. Area-array I/O presents new challenges to placement tools. Caldwell et al. =-=[9]-=- conducted a thorough study of the implication of area-array I/O for placement methods. They determined that with alternating I/O and core placement methods, whichKAHNG AND WANG: IMPLEMENTATION AND E... |

5 |
Function Smoothing with Applications to VLSI
- Baldick, Kahng, et al.
- 1999
(Show Context)
Citation Context ...ntly minimized. Convex nonlinear approximations of HPWL, which do not require net models and which permit direct inclusion of nonlinear delay terms, are proposed and well-studied in such works as [3] =-=[6]-=- [33] [34]. The approach of Naylor et al. [44] follows along similar lines, and uses a log-sumexp method to capture the linear half-perimeter wirelength while simultaneously obtaining the desirable ch... |

5 |
Linear Decomposition Algorithm for
- Li, Lillis, et al.
- 1995
(Show Context)
Citation Context ...id nodes is larger than 60. B. Wirelength Formulation Minimization of wirelength is a common objective for circuit placement. Linear and quadratic wirelength objectives are typically used; see, e.g., =-=[39]-=- and [51] for comparisons. The quadratic objective function is used in many analytical placement methods because it is continuously differentiable and can be minimized efficiently by solving a system ... |