DMCA
Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements (2005)
| Venue: | In DAC ’05: Proceedings of the 42nd annual conference on Design automation |
| Citations: | 14 - 0 self |
BibTeX
@INPROCEEDINGS{Heithecker05trafficshaping,
author = {Dipl. -ing Sven Heithecker},
title = {Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements},
booktitle = {In DAC ’05: Proceedings of the 42nd annual conference on Design automation},
year = {2005},
pages = {575--578},
publisher = {ACM Press}
}
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Abstract
Today high-end video and multimedia processing applications require huge amounts of memory. For cost reasons, the usage of conventional dynamic RAM (SDRAM) is preferred. However, SDRAM access optimization is a complex task, especially if multistream access with different QoS requirements is involved. In [8], a multi-stream DDR-SDRAM controller IP covering combinations of low latency requirements for processor cache access, hard realtime constraints for periodic video signals and hard real-time bursty accesses for video coprocessors was described. To handle these contradictory QoS requirements at high system performance, a combination of a 2-stage scheduling algorithm and static priorities were used. This paper describes an additional flow control which enhances the overall performance. Experiments with an FPGA based high-end video platform demonstrate the superiority of this architecture.
Keyphrases
sdram controller complex qos requirement contradictory qos requirement different qos requirement high-end video platform complex task static priority low latency requirement periodic video signal today high-end video additional flow control high system performance huge amount video coprocessors 2-stage scheduling algorithm multimedia processing application processor cache access overall performance hard real-time bursty access hard realtime constraint cost reason multi-stream ddr-sdram controller ip conventional dynamic ram multistream access sdram access optimization
