## 6.78 Gigabits per Second Implementation of the IDEA Cryptographic Algorithm (2002)

Venue: | Field-Programmable Logic and Applications – Reconfigurable Computing Is Going Mainstream, number 2438 in LNCS |

Citations: | 4 - 0 self |

### BibTeX

@INPROCEEDINGS{Hämäläinen026.78gigabits,

author = {Antti Hämäläinen and Matti Tommiska and Jorma Skyttä},

title = {6.78 Gigabits per Second Implementation of the IDEA Cryptographic Algorithm},

booktitle = {Field-Programmable Logic and Applications – Reconfigurable Computing Is Going Mainstream, number 2438 in LNCS},

year = {2002},

pages = {760--769},

publisher = {Springer}

}

### OpenURL

### Abstract

Abstract. IDEA (International Data Encryption Algorithm) is one of the strongest secret-key block ciphers. The algorithm processes data in 16-bit subblocks and can be fully pipelined. The implementation of a fully pipelined IDEA algorithm achieves a clock rate of 105.9 MHz on Xilinx ’ XCV1000E-6BG560 FPGA of the Virtex-E device family. The implementation uses 18105 logic cells and achieves a throughput of 6.78 Gbps with a latency of 132clock cycles. 1

### Citations

1098 |
Applied Cryptography
- Schneier
- 1993
(Show Context)
Citation Context ... multiplication; and if the result is 2 16 , replace this by 0. Decryption is achieved with the ciphertext Y provided as input M. Key scheduling is described in standard textbooks on cryptography [3] =-=[8]-=-, and its hardware requirements are negligible when compared to modulo (2 16 + 1) multipliers. 2.1 Diminished-One Number Representation The diminished-one number representation is often used in arithm... |

160 | A proposal for a new block encryption standard
- Lai, Massay
- 1962
(Show Context)
Citation Context ...cation, whereas the session specific secret keys are agreed on and distributed with a public key algorithm. The International Data Encryption Algorithm (IDEA) was introduced by Lai and Massay in 1990 =-=[1]-=-, and modified the following year [2]. IDEA has been patented in the U.S. and several European countries, but the non-commercial use of IDEA is free everywhere. The patent holder was originally Ascom ... |

115 | Markov ciphers and differential cryptanalysis
- Lai, Massey, et al.
- 1991
(Show Context)
Citation Context ...secret keys are agreed on and distributed with a public key algorithm. The International Data Encryption Algorithm (IDEA) was introduced by Lai and Massay in 1990 [1], and modified the following year =-=[2]-=-. IDEA has been patented in the U.S. and several European countries, but the non-commercial use of IDEA is free everywhere. The patent holder was originally Ascom AG, M. Glesner, P. Zipf, and M. Renov... |

88 |
Vanstone: Handbook of Applied Cryptography
- Menezes, Oorshcot, et al.
- 1997
(Show Context)
Citation Context ...8-bit key space, which is computationally infeasible. The security of IDEA appears bounded only by the weaknesses arising from the relatively small (compared to its keylength) blocklength of 64 bits. =-=[3]-=- Unlike many other cryptographic algorithms, IDEA can easily be implemented on 16-bit microcontrollers, since the algorithm operates on 16-bit subblocks. In 1999, a software-based implementation of fo... |

26 |
Regular VLSI-architectures for multiplication modulo (2n+1
- Curiger, Kaeslin
- 1991
(Show Context)
Citation Context ...plementation of IDEA is the modulo (2 16 + 1) multiplication operator. There has been a lot of academic activity in researching an optimum implementation of the modulo (2 16 +1)multiplier [12], [13], =-=[14]-=-, but the research has been limited to full-custom design. The partial product generation proposed by Ma [12] was used. The inputs to the partial product generation logic are 16-bit unsigned integers ... |

20 | A Cipher for Multimedia Architectures?,” Selected Areas in Cryptography ’98, LNCS 1556, Henk Meijer, Eds
- Lipmaa, “IDEA
- 1998
(Show Context)
Citation Context ...ubblocks. In 1999, a software-based implementation of four parallel IDEA algorithms (4-way IDEA) achieved a throughput of the order of 72 megabits per second (Mbps) on a 166 MHz MMX Pentium processor =-=[4]-=-. If this result is scaled to modern 2.533 GHz Pentium 4 processors, a software-based implementation of a 4-way IDEA achieves a throughput of 1.1 gigabits per second (1.1 Gbps). This sets a reference ... |

19 |
A simplified binary arithmetic for the Fermat number transform
- Leibowitz
- 1976
(Show Context)
Citation Context ...uirements are negligible when compared to modulo (2 16 + 1) multipliers. 2.1 Diminished-One Number Representation The diminished-one number representation is often used in arithmetic modulo (2 n + 1) =-=[9]-=-. In diminished-one number system the number A is represented by A ′ = A − 1 and the value 0 is represented by 2 n .InIDEA,n = 16, and consequentially, the value 0x0000 as a 16-bit unsigned integer is... |

18 | Fast implementations of secret-key block ciphers using mixed inner- and outer-round pipelining
- Chodowiec, Khuon, et al.
- 2001
(Show Context)
Citation Context ...ographic algorithms became feasible. If the entire algorithm with full inner and outer loop pipelining fits on a single FPGA, the limiting factor for throughput is the achieved clock rate as follows: =-=[10]-=- Throughput = block size × clock rate (1) Since the block size of IDEA is fixed at 64 bits, a 100 MHz clock rate implies a throughput of 6.4 Gbps. Clock rates above 100 MHz can be achieved in modern F... |

18 |
Efficient VLSI implementation of modulo (2 n ± 1) addition and multiplication
- Zimmermann
- 1999
(Show Context)
Citation Context ...are implementation of IDEA is the modulo (2 16 + 1) multiplication operator. There has been a lot of academic activity in researching an optimum implementation of the modulo (2 16 +1)multiplier [12], =-=[13]-=-, [14], but the research has been limited to full-custom design. The partial product generation proposed by Ma [12] was used. The inputs to the partial product generation logic are 16-bit unsigned int... |

9 |
A Simplified Architecture for Modulo (2 n + 1) Multiplication
- Ma
- 1998
(Show Context)
Citation Context ... at least 100 MHz, it was decided to recode the entire design in synthesisable VHDL with Synplify Pro 7.0. Investigating the critical path revealed that the carry-save adder (CSA) structure (See 3.2) =-=[12]-=- was the most time-consuming part. The CSA structure was replaced with a simple threestage adder tree, which both reduced area and increased the clock rate over thes6.78 Gbps Implementation of the IDE... |