6.78 Gigabits per Second Implementation of the IDEA Cryptographic Algorithm (2002)
| Venue: | Field-Programmable Logic and Applications – Reconfigurable Computing Is Going Mainstream, number 2438 in LNCS |
| Citations: | 4 - 0 self |
BibTeX
@INPROCEEDINGS{Hämäläinen026.78gigabits,
author = {Antti Hämäläinen and Matti Tommiska and Jorma Skyttä},
title = {6.78 Gigabits per Second Implementation of the IDEA Cryptographic Algorithm},
booktitle = {Field-Programmable Logic and Applications – Reconfigurable Computing Is Going Mainstream, number 2438 in LNCS},
year = {2002},
pages = {760--769},
publisher = {Springer}
}
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Abstract
Abstract. IDEA (International Data Encryption Algorithm) is one of the strongest secret-key block ciphers. The algorithm processes data in 16-bit subblocks and can be fully pipelined. The implementation of a fully pipelined IDEA algorithm achieves a clock rate of 105.9 MHz on Xilinx ’ XCV1000E-6BG560 FPGA of the Virtex-E device family. The implementation uses 18105 logic cells and achieves a throughput of 6.78 Gbps with a latency of 132clock cycles. 1
Citations
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