## Criticality computation in parameterized statistical timing (2006)

Venue: | in Proc. Design Automation Conf |

Citations: | 12 - 1 self |

### BibTeX

@INPROCEEDINGS{Xiong06criticalitycomputation,

author = {Jinjun Xiong and Vladimir Zolotov and Natesan Venkateswaran and Chandu Visweswariah},

title = {Criticality computation in parameterized statistical timing},

booktitle = {in Proc. Design Automation Conf},

year = {2006},

pages = {63--68},

publisher = {ACM Press}

}

### OpenURL

### Abstract

Chips manufactured in 90 nm technology have shown large parametric variations, and a worsening trend is predicted. These parametric variations make circuit optimization difficult since different paths are frequency-limiting in different parts of the multi-dimensional process space. Therefore, it is desirable to have a new diagnostic metric for robust circuit optimization. This paper presents a novel algorithm to compute the criticality probability of every edge in the timing graph of a design with linear complexity in the circuit size. Using industrial benchmarks, we verify the correctness of our criticality computation via Monte Carlo simulation. We also show that for large industrial designs with 442,000 gates, our algorithm computes all edge criticalities in less than 160 seconds.

### Citations

185 | Statistical Timing Analysis Considering Spatial Correlations Using a Single PERT-like Traversal
- Chang, Sapatnekar
(Show Context)
Citation Context ...tisfying timing, area, power and other design constraints. This goal can be achieved only by considering the whole space of process variations. Parameterized statistical static timing analysis (SSTA) =-=[5, 6]-=- provides that kind of exploration, computing the circuit delay as a function of process parameters. Unfortunately, knowing circuit delay is not enough. The optimization needs more detailed guidance t... |

140 | First-Order Incremental BlockBased Statistical Timing Analysis
- Visweswariah, Ravindran, et al.
(Show Context)
Citation Context ...tisfying timing, area, power and other design constraints. This goal can be achieved only by considering the whole space of process variations. Parameterized statistical static timing analysis (SSTA) =-=[5, 6]-=- provides that kind of exploration, computing the circuit delay as a function of process parameters. Unfortunately, knowing circuit delay is not enough. The optimization needs more detailed guidance t... |

125 |
The greatest of a finite set of random variables
- Clark
- 1961
(Show Context)
Citation Context ...ies to process parameters and statistical summation of uncorrelated terms. The maximum and minimum operations are approximated linearly using Clarkâs formulas and the concept of tightness probability =-=[11, 5, 6]-=-. Given two random variables D1 and D2, the tightness probability of D1 is the probability of D1 being greater than D2, i.e.,TD1=P (D1 >D2). If both D1 and D2 have normal distribution with means d1,0 ... |

124 |
Graph theory with application to engineering and computer science
- Deo
- 1974
(Show Context)
Citation Context ...e. In this paper, we develop an accurate and efficient technique for computing criticalities of timing edges in the context of parameterized block-based SSTA. We use the same concept of graph cutset =-=[9]-=- as [4] for computing timing yield gradient by perturbing PDFs of timing edges. Our computation uses only efficient operations of statistical minimum and maximum, and tightness probability computation... |

54 |
Parameterized Block-Based Statistical Timing Analysis with Non-Gaussian and
- Chang, Zolotov, et al.
- 2005
(Show Context)
Citation Context ... and Xr, respectively. All the sources of variation have independent Gaussian distributions with zero mean and unit variance. However, the proposed technique can be generalized to more complex models =-=[10]-=-. Signal propagation in parameterized SSTA is performed similarly to deterministic timing. The addition of first-order forms is performed by summing their corresponding sensitivities to process parame... |

52 | Death, taxes and failing chips
- Visweswariah
- 2003
(Show Context)
Citation Context ...1. INTRODUCTION As technology nodes shrink to 90 nm and below, it becomes more difficult to manufacture chips with guaranteed parametric timing yield due to substantial increase of process variations =-=[1]-=-. If these effects are not considered properly, the potential for silicon failure is high, and the associated cost for a design re-spin is prohibitive. Therefore, statistical methods have recently att... |

28 | Gate sizing using incremental parameterized statistical timing analysis
- Guthaus, Venkateswarann, et al.
(Show Context)
Citation Context ... to various combinations of process parameters. Deterministic optimization cannot guarantee that the chip satisfies design requirements for all or most of these combinations. Statistical optimization =-=[2, 3, 4]-=- is targeted to solve this problem. The goal of statistical optimization is to maximize yield while satisfying timing, area, power and other design constraints. This goal can be achieved only by consi... |

20 | Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations
- Li, Le, et al.
(Show Context)
Citation Context ...ticality of a path is the probability of manufacturing a chip in which the path is critical. The higher the criticality, the more important it is to improve the timing characteristics of the path. In =-=[8]-=- it is shown that the criticality of a path is equal to the sensitivity of the mean of the circuit delay with respect to the mean of the path delay. Often the concept of criticality is more convenient... |

19 | Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation
- Chopra, Shah, et al.
- 2005
(Show Context)
Citation Context ... to various combinations of process parameters. Deterministic optimization cannot guarantee that the chip satisfies design requirements for all or most of these combinations. Statistical optimization =-=[2, 3, 4]-=- is targeted to solve this problem. The goal of statistical optimization is to maximize yield while satisfying timing, area, power and other design constraints. This goal can be achieved only by consi... |

5 | Approximating the criticality indices of the activities - Dodin, Elmaghraby - 1985 |

2 |
Circuit optimization using statistical timing analysis
- Agarwal, Chopra, et al.
- 2005
(Show Context)
Citation Context ... to various combinations of process parameters. Deterministic optimization cannot guarantee that the chip satisfies design requirements for all or most of these combinations. Statistical optimization =-=[2, 3, 4]-=- is targeted to solve this problem. The goal of statistical optimization is to maximize yield while satisfying timing, area, power and other design constraints. This goal can be achieved only by consi... |