## Gate Sizing Using Incremental Parameterized Statistical Timing Analysis (2005)

Venue: | In ICCAD |

Citations: | 32 - 2 self |

### BibTeX

@INPROCEEDINGS{Guthaus05gatesizing,

author = {M. R. Guthaus and N. Venkateswaran and C. Visweswariah and V. Zolotov},

title = {Gate Sizing Using Incremental Parameterized Statistical Timing Analysis},

booktitle = {In ICCAD},

year = {2005},

pages = {1029--1036}

}

### OpenURL

### Abstract

Abstract — As technology scales into the sub-90nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as statistical distributions during both analysis and optimization. This paper uses incremental, parametric statistical static timing analysis (SSTA) to perform gate sizing with a required yield target. Both correlated and uncorrelated process parameters are considered by using a first-order linear delay model with fitted process sensitivities. The fitted sensitivities are verified to be accurate with circuit simulations. Statistical information in the form of criticality probabilities are used to actively guide the optimization process which reduces run-time and improves area and performance. The gate sizing results show a significant improvement in worst slack at 99.86 % yield over deterministic optimization. I.

### Citations

207 | Statistical timing analysis considering spatial correlations using a single pert-like traversal
- Chang, Sapatnekar
(Show Context)
Citation Context ...t runtime overhead is minimized by requiring only the necessary timing updates to satisfy a timing answer after a perturbation of the design. Recently, several methods for SSTA have been proposed [1]–=-=[4]-=-. The path-based methods, while they consider correlation due to re-convergent fanout and shared process parameters, are inherently not incremental. They require a run-time intensive integration over ... |

190 |
Tilos: A posynomial programming approach to transistor sizing
- Fishburn, Dunlop
- 1985
(Show Context)
Citation Context ...heuristic approaches to deterministic gate sizing have been proposed [11]–[14]. Algorithm 1 shows the implementation of a generic sensitivity-based sizing algorithm that is similar in spirit to TILOS =-=[12]-=-. The general idea of the algorithm is to start from minimum-sized gates, pick a set of candidate gates and try increasing each candidate gate one-ata-time. For each candidate, the circuit slack chang... |

176 |
Logical Effort: Designing Fast CMOS Circuits
- Sutherland, Sproull, et al.
- 1999
(Show Context)
Citation Context ... the timing constraint cannot be met, which is often the case, it is best to minimize the amount by which it fails. Many exact and heuristic approaches to deterministic gate sizing have been proposed =-=[11]-=-–[14]. Algorithm 1 shows the implementation of a generic sensitivity-based sizing algorithm that is similar in spirit to TILOS [12]. The general idea of the algorithm is to start from minimum-sized ga... |

159 | First-order incremental block-based statistical timing analysis
- Visweswariah, Ravindran, et al.
(Show Context)
Citation Context ...ation over the process space after every change. On the other hand, the block-based methods, while they are incremental, have not considered correlation. The block-based methods recently presented in =-=[3]-=- consider correlation yet retain incremental capabilities. Complementing the previous work on SSTA, some work has started to examine statistical optimization using non-incremental, non-parameterized S... |

140 |
The greatest of a finite set of random variables
- Clark
- 1961
(Show Context)
Citation Context ...A engine traverses the circuit network in breadthfirst topological order like DSTA. At each node, the mean and variance of the statistical maximum AT is efficiently calculated using analytic formulas =-=[15]-=-, [16]. The correlation coefficient is calculated from the covariance of the two canonical delays. Each output parameter sensitivity, si, is computed by linearly combining the delay sensitivities of t... |

123 | Statistical timing analysis for intra-die process variations with spatial correlations
- Agarwal, Blaauw, et al.
(Show Context)
Citation Context ...ly correlated among all gates whereas the last term is independent among all gates. The independent variable for intra-die modeling can be made less pessimistic as shown in previous publications [4], =-=[20]-=-, but that is not done in this paper. The nominal gate delay model considers the effects of both load capacitance and input slew rates on delay. V. STATISTICAL GATE SIZING Similar to deterministic gat... |

108 | An exact solution to the transistor sizing problem for CMOS circuit using convex optimization
- Sapatnekar, Rao, et al.
- 1993
(Show Context)
Citation Context ...timing constraint cannot be met, which is often the case, it is best to minimize the amount by which it fails. Many exact and heuristic approaches to deterministic gate sizing have been proposed [11]–=-=[14]-=-. Algorithm 1 shows the implementation of a generic sensitivity-based sizing algorithm that is similar in spirit to TILOS [12]. The general idea of the algorithm is to start from minimum-sized gates, ... |

58 | Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions
- Chang, Zolotov, et al.
(Show Context)
Citation Context ...e. The slack of the entire circuit is then measured at the virtual sink. For detailed explanation of the SSTA methodology and verification of the accuracy with monte carlo, please refer to [3], [17], =-=[18]-=-. B. Process Sensitivities The model for the delay variation coefficients, si, of the first-order parameterized model are now experimentally verified using Spice as in [19]. The variability parameters... |

55 |
Statistical Timing Analysis using Bounds and Selective Enumeration
- Agarwal, Zolotov, et al.
- 2002
(Show Context)
Citation Context ... that runtime overhead is minimized by requiring only the necessary timing updates to satisfy a timing answer after a perturbation of the design. Recently, several methods for SSTA have been proposed =-=[1]-=-–[4]. The path-based methods, while they consider correlation due to re-convergent fanout and shared process parameters, are inherently not incremental. They require a run-time intensive integration o... |

50 | Statistical timing for parametric yield prediction of digital integrated circuits
- Jess, Kalafala, et al.
(Show Context)
Citation Context ...that run-time overhead is minimized by requiring only the necessary timing updates to satisfy a timing answer after a perturbation of the design. Recently, several methods for SSTA have been proposed =-=[2, 13, 20, 5]-=-. The path-based methods, while they consider correlation due to reconvergent fanout and shared process parameters, are inherently not incremental. They require a run-time intensive integration over t... |

42 |
Optimization-based transistor sizing
- Shyu, Fishburn, et al.
- 1988
(Show Context)
Citation Context ...gcur 13: Sbest ⇐ Scur 14: end if 15: end for 16: Increase size of best gate, gbest 17: until Sbest = 0 or Slack ≥ 0 Many exact and heuristic approaches to deterministic gate sizing have been proposed =-=[18, 10, 16, 15]-=-. Algorithm 1sshows the implementation of a generic sensitivity-based sizing algorithm that is similar in spirit to TILOS [10]. The general idea of the algorithm is to start from minimum-sized gates, ... |

39 |
Gate sizing using a statistical delay model
- Jacobs, Berkelaar
- 2000
(Show Context)
Citation Context ...STA, some work has started to examine statistical optimization using non-incremental, non-parameterized SSTA. These works tend to only address random variation [5]–[9], use simplified heuristics [5], =-=[6]-=-, [8], [9], ignore path correlations [8], [9], or are too complex for large-scale optimization [10]. The contributions of this work can be summarized as the following: • This paper uses incremental SS... |

28 |
The Moment-Generating Function of the Minimum of Bivariate Normal Random Variables,” The American Statistician
- Cain
- 1994
(Show Context)
Citation Context ...ne traverses the circuit network in breadthfirst topological order like DSTA. At each node, the mean and variance of the statistical maximum AT is efficiently calculated using analytic formulas [15], =-=[16]-=-. The correlation coefficient is calculated from the covariance of the two canonical delays. Each output parameter sensitivity, si, is computed by linearly combining the delay sensitivities of the ATs... |

22 | Statistical optimization of leakage power considering process variations using dual-Vth and sizing
- Srivastava, Sylvester, et al.
(Show Context)
Citation Context ...l capabilities. Complementing the previous work on SSTA, some work has started to examine statistical optimization using nonincremental, non-parameterized SSTA. These works tend to ignore correlation =-=[8, 12, 17, 3, 14]-=-, use simplified heuristics [8, 12, 3, 14], ignore path correlations [3, 14], or are too complex for large-scale optimization [9]. The contributions of this work can be summarized as the following: • ... |

21 | Uncertainty-aware circuit optimization
- Bai, Visweswariah, et al.
- 2002
(Show Context)
Citation Context ...some work has started to examine statistical optimization using non-incremental, non-parameterized SSTA. These works tend to only address random variation [5]–[9], use simplified heuristics [5], [6], =-=[8]-=-, [9], ignore path correlations [8], [9], or are too complex for large-scale optimization [10]. The contributions of this work can be summarized as the following: • This paper uses incremental SSTA fo... |

21 | A new statistical optimization algorithm for gate sizing
- Mani, Orshansky
- 2004
(Show Context)
Citation Context ...Complementing the previous work on SSTA, some work has started to examine statistical optimization using non-incremental, non-parameterized SSTA. These works tend to only address random variation [5]–=-=[9]-=-, use simplified heuristics [5], [6], [8], [9], ignore path correlations [8], [9], or are too complex for large-scale optimization [10]. The contributions of this work can be summarized as the followi... |

15 |
Statistical integrated circuit design
- Director, Feldmann, et al.
- 1993
(Show Context)
Citation Context ...rized SSTA. These works tend to only address random variation [5]–[9], use simplified heuristics [5], [6], [8], [9], ignore path correlations [8], [9], or are too complex for large-scale optimization =-=[10]-=-. The contributions of this work can be summarized as the following: • This paper uses incremental SSTA for circuit optimization while considering multiple correlated and independent sources of variat... |

4 | Variability inspired implementation selection problem
- Davoodi, Khandelwal, et al.
- 2004
(Show Context)
Citation Context ...es. Complementing the previous work on SSTA, some work has started to examine statistical optimization using non-incremental, non-parameterized SSTA. These works tend to only address random variation =-=[5]-=-–[9], use simplified heuristics [5], [6], [8], [9], ignore path correlations [8], [9], or are too complex for large-scale optimization [10]. The contributions of this work can be summarized as the fol... |

3 | Optimization objectives and models of variation for statistical gate sizing
- Guthaus, Venkateswaran, et al.
(Show Context)
Citation Context ... please refer to [3], [17], [18]. B. Process Sensitivities The model for the delay variation coefficients, si, of the first-order parameterized model are now experimentally verified using Spice as in =-=[19]-=-. The variability parameters are assumed to be fully correlated within a gate. In general, every gate arc could have an arbitrary sensitivity that is derived from the transistor widths, gate load, and... |

1 |
Dockets YOR9-2003-401 &YOR9-2003-402 & YOR9-2003-403, Filed with the U.S. Patent Office
- Visweswariah
- 2003
(Show Context)
Citation Context ...up time. The slack of the entire circuit is then measured at the virtual sink. For detailed explanation of the SSTA methodology and verification of the accuracy with monte carlo, please refer to [3], =-=[17]-=-, [18]. B. Process Sensitivities The model for the delay variation coefficients, si, of the first-order parameterized model are now experimentally verified using Spice as in [19]. The variability para... |