## A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing

Citations: | 6 - 2 self |

### BibTeX

@MISC{Chu_apolynomial,

author = {Chris C. N. Chu and et al.},

title = {A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing},

year = {}

}

### OpenURL

### Abstract

An interconnect joining a source and a sink is divided into fixed-length uniform-width wire segments, and some adjacent segments have buffers in between. The problem we considered is to simultaneously size the buffers and the segments so that the Elmore delay from the source to the sink is minimized. Previously, no polynomial time algorithm for the problem has been reported in literature. In this paper, we present a polynomial time algorithm SBWS for the simultaneous buffer and wire sizing problem. SBWS is an iterative algorithm with guaranteed convergence to the optimal solution. It runs in quadratic time and uses constant memory for computation. Also, experimental results show that SBWS is extremely efcient in practice. For example, for an interconnect of 10000 segments and buffers, the CPU time is only 0.127 second.

### Citations

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(Show Context)
Citation Context ...wnstream capacitances of component i be Ci if i 2B,orCi+fi=2 if i 2W. (source) Ri-1 Ci-1 RiCi Component i Figure 4: Illustration of Ri and Ci. (sink) In this paper, the widely used Elmore delay model =-=[13]-=- is used for delay calculation. Basically, the Elmore delay from the source to the sink is the sum of the delays associated with the components, where the delay associated with a component is equal to... |

105 | Performance optimization of VLSI interconnect layout
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(Show Context)
Citation Context ...hnology. Interconnect delay has become the dominating factor in determining system performance. In many systems designed today, as much as 50% to 70% of clock cycle are consumed by interconnect delay =-=[8]-=-. It is predicted in [11] that the feature size will be reduced to 0:18 m by 1999 and 0:13 m by 2002. So we expect the signi cance of interconnect delay will further increase in the near future. Both ... |

56 | Optimal wiresizing under the distributed Elmore delay model
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(Show Context)
Citation Context ...ease in the near future. Both bu er sizing and wire sizing have been shown to be e ective techniques to reduce interconnect delay and many works have been done during the past few years. For example, =-=[2, 3, 4,10,14]-=- are various results on wire sizing alone. [16] applies the sequential quadratic programming approach to simultaneous gate and wire sizing. This algorithm is comparatively slow asithasto solve a seque... |

49 |
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Citation Context ...2W, then we can write D in (3) in term of xi as D = Ri,1bcixi + bri xi So @D=@xi = 0 is equivalent to (Ci + fi ) + terms independent ofxi 2 bciRi,1x 2 i = bri(Ci+fi=2) (9) Note that D is a posynomial =-=[12]-=- in x1;:::;xn. It is well known that under a variable transformation, a posynomial is equivalent to a convex function. So D has a unique global minimum and no other local minimum. That means, if for s... |

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Citation Context ... have been shown to be e ective techniques to reduce interconnect delay and many works have been done during the past few years. For example, [2, 3, 4,10,14] are various results on wire sizing alone. =-=[16]-=- applies the sequential quadratic programming approach to simultaneous gate and wire sizing. This algorithm is comparatively slow asithasto solve a sequence of quadratic programming subproblems. This ... |

23 | Optimal wire-sizing function with fringing capacitance consideration
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(Show Context)
Citation Context ...ease in the near future. Both bu er sizing and wire sizing have been shown to be e ective techniques to reduce interconnect delay and many works have been done during the past few years. For example, =-=[2, 3, 4,10,14]-=- are various results on wire sizing alone. [16] applies the sequential quadratic programming approach to simultaneous gate and wire sizing. This algorithm is comparatively slow asithasto solve a seque... |

22 | Optimal NonUniform Wire-Sizing Under the Elmore Delay Model
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(Show Context)
Citation Context ...ease in the near future. Both bu er sizing and wire sizing have been shown to be e ective techniques to reduce interconnect delay and many works have been done during the past few years. For example, =-=[2, 3, 4,10,14]-=- are various results on wire sizing alone. [16] applies the sequential quadratic programming approach to simultaneous gate and wire sizing. This algorithm is comparatively slow asithasto solve a seque... |

19 | Shaping a VLSI wire to minimize Elmore delay
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(Show Context)
Citation Context |

19 |
Optimal wire sizing and buer insertion for low power and a generalized delay model
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(Show Context)
Citation Context ...s work was partially supported by the Texas Advanced Research Program under Grant No. 003658288 and by a grant from the Intel Corporation. Also, no bound on the run time of the algorithm is reported. =-=[15]-=- gives an algorithm for simultaneous bu er insertion, bu er sizing and wire sizing based on dynamic programming. However, their algorithm runs in pseudopolynomial time and requires a substantial amoun... |

15 |
A Fast Algorithm for Optimal Wire-Sizing Under Elmore Delay Model
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(Show Context)
Citation Context |

10 |
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(Show Context)
Citation Context ...orithm for simultaneous bu er insertion, bu er sizing and wire sizing based on dynamic programming. However, their algorithm runs in pseudopolynomial time and requires a substantial amount of memory. =-=[1, 7, 9]-=-give greedy algorithms for simultaneous transistor/bu er and wire sizing. These algorithms are shown to be very e cient in practice. However, no bounds on the run time of them are known. [5] considers... |

7 |
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(Show Context)
Citation Context ...orithm for simultaneous bu er insertion, bu er sizing and wire sizing based on dynamic programming. However, their algorithm runs in pseudopolynomial time and requires a substantial amount of memory. =-=[1, 7, 9]-=-give greedy algorithms for simultaneous transistor/bu er and wire sizing. These algorithms are shown to be very e cient in practice. However, no bounds on the run time of them are known. [5] considers... |

6 |
Closed form solution to simultaneous bu er insertion/sizing and wire sizing
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(Show Context)
Citation Context ...ry. [1, 7, 9]give greedy algorithms for simultaneous transistor/bu er and wire sizing. These algorithms are shown to be very e cient in practice. However, no bounds on the run time of them are known. =-=[5]-=- considers bu er insertion, bu er sizing and wire sizing simultaneously and a closed form optimal solution is obtained. However, in that paper, only wire area capacitance is considered. Wire fringing ... |

6 |
A new approach to simultaneous buer insertion and wire sizing
- Chu, Wong
- 1997
(Show Context)
Citation Context ...ecome more and more signi cant as feature size decreases, is ignored. Taking wire fringing capacitance into account signi cantly complicates the problem and [5] can only give an approximate solution. =-=[6]-=- shows that the simultaneous bu er insertion and wire sizing problem can be formulated as a convex quadratic program. The convex quadratic program has a small size and some special structures, and so ... |

3 |
Advances outpace SIA roadmap (Semiconductor Industry Association alters projections) (Industry Trend or Event
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(Show Context)
Citation Context ...lay has become the dominating factor in determining system performance. In many systems designed today, as much as 50% to 70% of clock cycle are consumed by interconnect delay [8]. It is predicted in =-=[11]-=- that the feature size will be reduced to 0:18 m by 1999 and 0:13 m by 2002. So we expect the signi cance of interconnect delay will further increase in the near future. Both bu er sizing and wire siz... |

1 |
An e cient approach tosimultaneous transistor and interconnect sizing
- Cong, He
- 1996
(Show Context)
Citation Context ...orithm for simultaneous bu er insertion, bu er sizing and wire sizing based on dynamic programming. However, their algorithm runs in pseudopolynomial time and requires a substantial amount of memory. =-=[1, 7, 9]-=-give greedy algorithms for simultaneous transistor/bu er and wire sizing. These algorithms are shown to be very e cient in practice. However, no bounds on the run time of them are known. [5] considers... |