## Performance optimization of VLSI interconnect layout (1996)

### Cached

### Download Links

Venue: | Integration, the VLSI Journal |

Citations: | 102 - 32 self |

### BibTeX

@ARTICLE{Cong96performanceoptimization,

author = {Jason Cong and Lei He and Cheng-kok Koh and Patrick H. Madden},

title = {Performance optimization of VLSI interconnect layout},

journal = {Integration, the VLSI Journal},

year = {1996},

volume = {21},

pages = {1--94}

}

### Years of Citing Articles

### OpenURL

### Abstract

This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for high-performance VLSI circuit design under the deep submicron fabrication technologies. First, we present a number of interconnect delay models and driver/gate delay models of various degrees of accuracy and efficiency which are most useful to guide the circuit design and interconnect optimization process. Then, we classify the existing work on optimization of VLSI interconnect into the following three categories and discuss the results in each category in detail: (i) topology optimization for highperformance interconnects, including the algorithms for total wire length minimization, critical path length minimization, and delay minimization; (ii) device and interconnect sizing, including techniques for efficient driver, gate, and transistor sizing, optimal wire sizing, and simultaneous topology construction, buffer insertion, buffer and wire sizing; (iii) highperfbrmance clock routing, including abstract clock net topology generation and embedding, planar clock routing, buffer and wire sizing for clock nets, non-tree clock routing, and clock schedule optimization. For each method, we discuss its effectiveness, its advantages and limitations, as well as its computational efficiency. We group the related techniques according to either their optimization techniques or optimization objectives so that the reader can easily compare the quality and efficiency of different solutions.

### Citations

1466 | A note on two problems in connexion with graphs, Numerische Mathematik 1
- Dijkstra
- 1959
(Show Context)
Citation Context ...nce of constructing a minimum-cost shortest path tree. For a shortest paths spanning tree construction, the classical method by Dijkstra can be used to construct a shortest paths tree (SPT) in a graph=-=[Di59]-=-, in which every vertex is connected to the root (or source) by a shortest path. While the original algorithm only ensures that all paths are shortest paths, it can be easily modified to construct the... |

830 | A note on the two problems in connections with graphs. Nummerische Mathematik 1 - Dijkstra - 1959 |

774 |
An algorithm for least-squares estimation of nonlinear parameters
- Marquardt
- 1963
(Show Context)
Citation Context ...problem aims to assign widths to the m wires in the general network such that the sum of squares of error f(w 1 ; w 2 ; :::; wm ) =sn i=1 g 2 i is minimized. The OSM uses the Gauss-Marquardt's method =-=[Ma63]-=- to solve the optimization problem. The Gauss-Marquardt's method takes an initial wire width assignment, W i and compute a new wire width assignment W i+1 based on a n \Theta m delay sensitivity matri... |

436 |
Circuits, Interconnections and Packaging for VLSI
- Bakoglu
- 1990
(Show Context)
Citation Context ... will reach 64 million in Year 2001 [SIA94]. Second, the devices operate at a higher speed, and the interconnect delay becomes much more significant. According to the simple scaling rule described in =-=[Ba90]-=-, when the devices and interconnects are scaled down in all three dimensions by a factor of S, the intrinsic gate delay is reduced by a factor of S, the delay of local interconnects (such as connectio... |

417 |
Introduction to VLSI systems
- Mead, Conway
- 1980
(Show Context)
Citation Context ...It is minimized when f ln( f ) is minimum, which leads to f = e, the base of natural logarithms. This is the well known optimal stage ratio for delay minimization presented in most textbooks (such as =-=[MeCo93]-=-). The output capacitance of a driver is not considered in the above derivation. In [HeJe87], a more accurate analytical delay formula was developed with consideration of the input waveform slope and ... |

390 |
Asymptotic waveform evaluation for timing analysis
- Pillage, Rohrer
- 1990
(Show Context)
Citation Context ...t shortcoming of the Elmore delay model and other simpler delay models is that they cannot handle the inductance effect. The Asymptotic Waveform Evaluation (AWE) method proposed by Pillage and Rohrer =-=[PiRo90]-=- is an efficient technique to use higher order moments in interconnect timing analysis which can handle the inductance effect. It constructs a q-pole transfer functionsH(s), called the q-pole model,sH... |

368 | The Transient Response of Damped Linear Networks With Particular Regard to Wide-Band Ampli - Elmore - 1948 |

350 |
Steiner tree problems
- Hwang, Richards
- 1992
(Show Context)
Citation Context ...e the VLSI design community, and goes well beyond the scope of this paper. We will discuss several typical and commonly used algorithms here, and recommend a more detailed survey by Hwang and Richards=-=[HwRi92]-=- to the interested reader. The Steiner problem is defined as follows: Given a set P of n points, find a set S of Steiner points such that MST(P S S) has the minimum cost. For interconnect optimization... |

317 |
Combinational profiles of sequential benchmark circuits
- Brglez, Bryan, et al.
- 1989
(Show Context)
Citation Context ...nt perturbation operation, the UST algorithm performs gate sizing of combinational logic blocks to reduce power dissipation. The UST heuristic has been evaluated using three ISCAS89benchmark circuits =-=[BrBK89]-=- and two industry circuits. In all but one case, the UST algorithm uses less wirelength when compared to the Greedy-BST/DME [CoKo95, HuKT95] and BB+DME algorithms [ChHH92b]. For each circuit, the skew... |

242 | SPICE2: A Computer Program to Simulate Semiconductor Circuits - Nagel - 1975 |

197 |
and K.Eshraghian. Principles of CMOS VLSI Design: A Systems Perspective
- Weste
- 1988
(Show Context)
Citation Context ... is the input rise or fall time. We first use a transistor to illustrate the simple switch-level RC model, where a transistor is modeled as an effective resistance discharging or charging a capacitor =-=[WeEs93]-=-. Figure 3(a) shows a simple switch-level RC model of an n-transistor. Let the minimum n-transistor resistance be R n . The gate capacitance and output diffusion capacitance of the minimum n-transisto... |

181 | Signal Delay in RC Tree Networks
- Rubinstein, Pen, et al.
- 1983
(Show Context)
Citation Context ...the remainder of this section consider both wire resistance and capacitance of the interconnect. Under these models, the interconnect is modeled as an RC tree, which is recursively defined as follows =-=[RuPH83]-=-: (i) a lumped capacitor between ground and another node is an RC tree, (ii) a lumped resistor between two nonground nodes is an RC tree, (iii) an RC line with no dc path to ground is an RC tree, and ... |

167 |
TILOS: A posynomial programming approach to transistor sizing,” ICCAD, Nov 1985 [11] A. Dharchoudhury, et al., “Fast and accurate timing simulation with regionwise quadratic models
- Fishburn
- 1994
(Show Context)
Citation Context ...e gate sizing problem has been classified into both continuous and discrete gate sizing problems, and solved by different approaches. 4.1.2. l. Sensitivity-based transistor sizing Fishburn and Dunlop =-=[81]-=- studied the transistor sizing problems for synchronous MOS circuits. Let x .... ,x,...,x,, be the transistor sizes, A the total active area of transistors and T the clock period. If K is a positive c... |

162 |
Short-Circuit Dissipation of Static CMOS Circuitry and its Impact on the Design of Buffer Circuits
- Veendrick
- 1984
(Show Context)
Citation Context ...tion. We would like to point out that all studies in [77, 35, 79] also discussed the optimal driver sizing for power minimization. Another study on optimal driver sizing for low power can be found in =-=[80]-=-. 4.1.2. Transistor and gate sizing In addition to sizing drivers which usually drive global interconnects, the sizes of all transistors and gates in the entire circuit or a subcircuit can also be adj... |

144 | A Note on Two - Dijkstra - 1959 |

140 |
Clock Skew Optimization
- Fishburn
- 1990
(Show Context)
Citation Context ...different combinational logic blocks 82 are likely to be different). There are several works on clock schedule optimization. However, these works did not consider clock routing. For example, Fishburn =-=[Fi90]-=- used linear programming to compute the optimal clock arrival times at the sinks such that either the clock period C P is minimized or the safety margin for clock error given a prescribed clock period... |

139 |
On Steiner’s problem with rectilinear distance
- Hanan
- 1966
(Show Context)
Citation Context ... heuristics for the rectilinear distance metric, which is most relevant to VLSI interconnect design. Clearly the set of potential Steiner points is infinite. For the rectilinear metric, however, Hanan=-=[Ha66] showed th-=-at the set of Steiner points which need to be considered in the construction of a SMT can be limited to the "Hanan grid," formed by the intersections of vertical and horizontal lines through... |

120 |
A new algorithm for minimizing convex functions over convex sets
- Vaidya
- 1996
(Show Context)
Citation Context ...ce the Elmore delay of the previous stage. Under the delay model, the transistor sizing problem is a posynomial program that can be transformed into a convex program and the convex programming method =-=[92]-=- was implemented to solve the transformed problem. When using the simple delay model of TILOS [81], and the timing specification is loose, the area of the solution obtained by TILOS is close to that o... |

109 | Packaging for VLSI - Bakoglu, Circuits - 1990 |

106 | Optimal wire sizing and buffer insertion for low power and a generalized delay model
- Lillis, Cheng, et al.
- 1995
(Show Context)
Citation Context ...circuits implemented by complex gates. 4.3.4 Simultaneous Buffer Insertion and Wire Sizing The polynomial-time dynamic programming algorithm for the buffer insertion problem [va90] was generalized in =-=[LiCL95]-=- to handle the simultaneous wiresizing and buffer insertion for both delay and power minimization. The slope effect on the buffer delay was also taken into account. Only the delay minimization feature... |

104 |
On Steiner minimal trees with rectilinear distance
- Hwang
- 1976
(Show Context)
Citation Context ...mshave exponential complexity and are applicable to only small problems. Given that construction of an optimal SMT is NP-hard, it is natural to look for heuristics. An interesting result, due to Hwang=-=[Hw76]-=-, is that the ratio of tree lengths between a rectilinear MST and a rectilinear SMT is no worse than 3 2 . The bounded performance of MST constructions has made the Prim and Kruskal algorithms popular... |

91 | A new class of iterative steiner tree heuristics with good performance. IEEETrans
- Kahng, Robins
- 1992
(Show Context)
Citation Context ...ment of an MST through edge merging can be effective at minimizing tree length on average, there exist pathological cases in which merge-based Steiner heuristics can exhibit the worstcase performance =-=[51]-=-. In Fig. 9, one such case is shown. For this point set, the tree constructed by any MST algorithm is unique. Traditional merge-based heuristics have relatively little gain, as only the three leftmost... |

90 | An exact solution to the transistor sizing problem for CMOS circuits using convex optimization
- Sapatnekar, Rao, et al.
- 1993
(Show Context)
Citation Context ...S, thus it is still possible to lose the optimal solution with respect to the whole circuit. Experimental results of circuits with up to 500 transistors have been presented. More recently, Sapatnekar =-=[SaRV93]-=- developed a transistor sizing tool iCONTRAST, again, to minimize the circuit area under timing constraints. It employs the analytical delay model developed in [HeJe87] which can consider the waveform... |

81 | Ginneken, “Buffer placement in distributed RC-tree network for minimal Elmore delay - van - 1990 |

80 |
On Optimal Interconnections for VLSI
- Kahng, Robins
- 1995
(Show Context)
Citation Context ...) Embedding of abstract topology, (iii) Planar routing, (iv) Buffer and wire sizing, (v) Non-tree clock routing, and (vi) Clock schedule optimization. Many results in (i)--(iii) were also surveyed in =-=[KaRo94]-=-. While we aim to cover all recent works on interconnect design and optimization in high performance clock routing in this section, this is not a comprehensive survey on clock synthesis and we left ou... |

79 | CMOS Circuit Speed and Buffer Optimization - Hedenstierna, Jeppson - 1987 |

75 | Provably good performance-driven global routing
- Cong, Kahng, et al.
- 1992
(Show Context)
Citation Context ...ith low average wire length and bounded path length, pathological cases exist where the tree cost is not bounded. In order to compute a spanning tree with bounded radius and bounded cost, Cong et al. =-=[58]-=- extended the shallow-light tree construction by Awerbuch el al. [59], which was originally designed for communications protocols. The algorithm of [59] constructs spanning trees which have bounded pe... |

74 | Zero skew clock routing with minimum wirelength
- Chao, Hsu, et al.
- 1992
(Show Context)
Citation Context ...ee ISCAS89benchmark circuits [BrBK89] and two industry circuits. In all but one case, the UST algorithm uses less wirelength when compared to the Greedy-BST/DME [CoKo95, HuKT95] and BB+DME algorithms =-=[ChHH92b]-=-. For each circuit, the skew bound for BST construction [CoKo95, HuKT95] is set to be the smallest skew bound of all sink pairs. To compare the impact of a UST on power dissipation, [XiDa96] also perf... |

72 |
Approximation of Wiring Delay in MOSFET LSI
- Sakurai
- 1983
(Show Context)
Citation Context ...he target sink. The target sink was selected to minimize the distance between the sink and the partial tree. The algorithm uses the A* search technique, with delay calculated by a method described in =-=[Sa83]-=-. In [HoXK93], Hong et al. propose two tree construction methods. The first, called the Iterative Dreyfus-Wagner (IDW) Steiner tree algorithm. This method modifies the optimal Steiner tree constructio... |

70 |
Buffer Placement in Distributed RC-Tree Networks for Minimal Elmore Delay
- GINNEKEN
- 1990
(Show Context)
Citation Context ...rconnect line, respectively, and R0 and Co the driver resistance and the input capacitance of the minimum-size inverter, respectively. A polynomial-time dynamic programming algorithm was presented in =-=[107]-=- to find the optimal buffer placement and sizing br RC trees under the Elmore delay model. The formulation assumes that the possible buffer positions (called legal positions), possible buffer sizes, a... |

67 | Performance-driven interconnect design based on distributed RC delay model
- Cong, Leung, et al.
- 1993
(Show Context)
Citation Context ...bjectives are constructions which provide shortest paths from the source to sink nodes. While this clearly minimizes path resistances, we also want to minimize the total tree capacitance. Cong et al. =-=[41]-=- showed that a minimum-cost shortest path tree is very useful for delay minimization. Given a routing tree T, they decomposed the upper bound signal delay tp at any node in T under the Rubinstein et a... |

65 | Generation of performance constraints of layout - Nair, Berman, et al. - 1989 |

62 |
Modeling the “Effective capacitance” for the RC interconnect of CMOS gates
- Qian, Pullela, et al.
- 1994
(Show Context)
Citation Context ... driver delay model precharactefizes the driver delay of each type of gate/buffer in terms of the input transition time 4, and the total load capacitance CL in the following forms of k/ctor equations =-=[34, 38]-=-: t01' (kl d- k2CL)4 +k3C --k4C I +ks, where k...s and k(... s are determined based on detailed circuit simulation (e.g. using SPICE [13]) and linear regression or least-squares fits. Similar k-hctor ... |

61 |
Exact Zero Skew
- Tsay
- 1991
(Show Context)
Citation Context ...le, Figure 25(a) plots HSPICE delay skew against pathlength delay skew for routing trees generated by the Greedy-BST/DME algorithm under pathlength delay [CoKo95, HuKT95] on MCNC benchmark circuit r3 =-=[Ts91]-=-. Not only is the correlation poor, but the pathlength-based BST solutions simply cannot meet tight skew bounds (of 100ps or less). On the other hand, Figure 25(b) demonstrates the accuracy and fideli... |

60 |
Cost-sensitive analysis of communication protocols
- Awerbuch, Peleg
- 1990
(Show Context)
Citation Context ... tree cost is not bounded. In order to compute a spanning tree with bounded radius and bounded cost, Cong et al.[CoKR92] extended the shallow-light 22 tree construction by Awerbuch, Baratz, and Peleg =-=[AwBP90]-=-, which was originally designed for communications protocols. The algorithm of [AwBP90] constructs spanning trees which have bounded performance for both total tree length and also maximum diameter. T... |

58 | Buffered steiner tree construction with wire sizing for interconnect layout optimization
- Okamoto, Cong
- 1996
(Show Context)
Citation Context ...elay also has the maximum skew, minimization of the maximum delay also minimizes the maximum skew. 4.4.2 Simultaneous Tree Construction, Buffer Insertion and Wiresizing Most recently, Okamoto and Cong=-=[OkCo96b]-=- study the simultaneous tree construction, buffer insertion and wiresizing problem 10 . The following techniques are combined to develop a wiresized buffered A-tree (WBA-tree) algorithm: the A-tree al... |

53 | Optimal wiresizing under the distributed elmore delay model
- Cong, Leung
- 1993
(Show Context)
Citation Context ...erconnect tree as an RC tree: (a) an interconnect tree, (b) each edge is modeled as a n-type circuit, and (c) each edge is modeled as an RC line. w,, and the parasitics of the interconnect as follows =-=[7, 8]-=-: t(so, si)sr,(c,,/'2 + Cap(v)) e CPath( , s ) Z 2 ,,, GPath(,0,3, ) 2 e, GPath(.%,s, ) 147e, le,,I e, C Path(so. s, ) e,, Des(e, ) le41e,,I le,-I +rcrs-- +r Zsc,--, (3) ersPath(,s',us.. ) e,,&l)esle,... |

51 | Near-optimal critical sink routing tree constructions
- Boese, Kahng, et al.
- 1993
(Show Context)
Citation Context ...RT constructions were very close to those of BB-SORT constructions. For random problems with 9 points, using 0.5 },t CMOS IC parameters, the SERT delays were only 3.9% above those of BB-SORT [10]. In =-=[72]-=-, it was also shown that the trees constructed using the Elmore delay model as an objective provided good performance under SPICE simulation. The authors enumerated all possible topologies for small n... |

51 | Zero-Skew Clock Routing Trees With Minimum Wirelength
- Boese, Kahng
- 1992
(Show Context)
Citation Context ...ing of Abstract Topology Given a prescribed abstract topology, the Deferred-Merge Embedding (DME) algorithm, proposed independently by Edahiro [Ed91], Chao, Hsu, and Ho [ChHH92a], and Boese and Kahng =-=[BoKa92]-=-, achieves exact zero skew for both pathlength and Elmore delay models. The enabling concept is that of a merging segment. The problem of bounded-skew embedding was first addressed independently by Co... |

51 | Minimum crosstalk channel routing - Gao, Liu - 1993 |

50 | Simultaneous driver and wire sizing for performance and power optimization
- Cong, Koh
- 1994
(Show Context)
Citation Context ...ivision. In addition to replacing the GWSA algorithm in both the single-source and multi-source wire-sizing problems, the BWSA algorithm can be used in the simultaneous driver and wire-sizing problem =-=[8]-=- to be presented in Section 4.3.1. 4.2.1.4. Continuous and non-untform wire-sizing jbr single-source RC tree Another alternative to achieve non-uniform wire width within a segment is the optimal wire-... |

50 | Modeling the drivingpoint characteristic of resistive interconnect for accurate delay estimation - O’Brien, Savarino - 1989 |

50 |
Zero Skew Clock Net Routing
- Chao, Hsu, et al.
- 1992
(Show Context)
Citation Context ...f routing alternatively between the horizontal and vertical directions, the MMM method is also extended to allow one level of "look-ahead" to determine the more favorable direction. Chao, Hs=-=u, and Ho [ChHH92a]-=- presented another top-down topology generation approach called the Balanced Bipartition (BB) method. The heuristic divides the sink set recursively into two partitions with nearly equal total loading... |

50 | Timing models for MOS circuits - Horowitz - 1984 |

48 | New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing
- Lillis, Cheng, et al.
- 1996
(Show Context)
Citation Context ...to the heuristic of [64], described in Section 3.2.2. Afterwards, a post-processing procedure is applied to perform heuristic local optimization to further minimize the delay. Recently, Lillis et al. =-=[74]-=- addressed performance driven interconnect topology problem through the construction of Permutation-constrained Routing Trees or P-Trees. Their algorithm first constructs a MST for the point set, and ... |

48 |
Clock Routing for High Performance ICs
- Jackson, Srinivasan, et al.
- 1990
(Show Context)
Citation Context ...vely high for large clock nets, impacting circuit area, power consumption, and clock rates for large circuits. The Method of Means and Medians (MMM) algorithm proposed by Jackson, Srinivasan, and Kuh =-=[JaSK90]-=- generalizes the H-tree algorithm; the idea is to perform partitioning along x and y directions alternatively. Given a set of sinks S = fs 1 ; s 2 ; \Delta \Delta \Delta ; s n g to be partitioned, the... |

46 | RC interconnect optimization under the Elmore delay model - Sapatnekar - 1994 |

44 | Optimal Wire-Sizing Formula Under the Elmore Delay Model
- Chen, Chen, et al.
- 1996
(Show Context)
Citation Context ... between multiple source-sink pairs. Wiresizing works in [CoLe93, CoLe95, CoHe95, CoHe96a] assumed that the wire widths are discrete and uniform within a wire segment or sub-segment. Most recently in =-=[ChCW96b]-=-, an optimal wire-sizing formula was derived by Chen et al. to achieve the continuous and non-uniform wire width for each wire segment, again to minimize the weighted combination of Elmore delays from... |

44 | High-Performance Clock Routing Based on Recursive Geometric Matching - Kahng, Cong, et al. - 1991 |

42 |
An edge-based heuristic for Steiner routing
- Borah, Owens, et al.
- 1994
(Show Context)
Citation Context ...tation is O(n3), while a naive approach may be O(nS); this may make it impractical for problems with large numbers of vertices. The third approach we discuss is an MST-based heuristic by Borah et al. =-=[55]-=-. It produces results that are comparable to the 1-Steiner algorithm, but with a complexity of only O(n:). Rather than optimizing a MST by merging edges, their method improves an initial MST by findin... |