## Performance optimization of VLSI interconnect layout (1996)

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Venue: | Integration, the VLSI Journal |

Citations: | 105 - 32 self |

### BibTeX

@ARTICLE{Cong96performanceoptimization,

author = {Jason Cong and Lei He and Cheng-kok Koh and Patrick H. Madden},

title = {Performance optimization of VLSI interconnect layout},

journal = {Integration, the VLSI Journal},

year = {1996},

volume = {21},

pages = {1--94}

}

### Years of Citing Articles

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### Abstract

This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for high-performance VLSI circuit design under the deep submicron fabrication technologies. First, we present a number of interconnect delay models and driver/gate delay models of various degrees of accuracy and efficiency which are most useful to guide the circuit design and interconnect optimization process. Then, we classify the existing work on optimization of VLSI interconnect into the following three categories and discuss the results in each category in detail: (i) topology optimization for highperformance interconnects, including the algorithms for total wire length minimization, critical path length minimization, and delay minimization; (ii) device and interconnect sizing, including techniques for efficient driver, gate, and transistor sizing, optimal wire sizing, and simultaneous topology construction, buffer insertion, buffer and wire sizing; (iii) highperfbrmance clock routing, including abstract clock net topology generation and embedding, planar clock routing, buffer and wire sizing for clock nets, non-tree clock routing, and clock schedule optimization. For each method, we discuss its effectiveness, its advantages and limitations, as well as its computational efficiency. We group the related techniques according to either their optimization techniques or optimization objectives so that the reader can easily compare the quality and efficiency of different solutions.

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Citation Context ...t shortcoming of the Elmore delay model and other simpler delay models is that they cannot handle the inductance effect. The Asymptotic Waveform Evaluation (AWE) method proposed by Pillage and Rohrer =-=[PiRo90]-=- is an efficient technique to use higher order moments in interconnect timing analysis which can handle the inductance effect. It constructs a q-pole transfer functionsH(s), called the q-pole model,sH... |

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Citation Context ...the remainder of this section consider both wire resistance and capacitance of the interconnect. Under these models, the interconnect is modeled as an RC tree, which is recursively defined as follows =-=[RuPH83]-=-: (i) a lumped capacitor between ground and another node is an RC tree, (ii) a lumped resistor between two nonground nodes is an RC tree, (iii) an RC line with no dc path to ground is an RC tree, and ... |

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Citation Context ...S, thus it is still possible to lose the optimal solution with respect to the whole circuit. Experimental results of circuits with up to 500 transistors have been presented. More recently, Sapatnekar =-=[SaRV93]-=- developed a transistor sizing tool iCONTRAST, again, to minimize the circuit area under timing constraints. It employs the analytical delay model developed in [HeJe87] which can consider the waveform... |

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Citation Context ...ee ISCAS89benchmark circuits [BrBK89] and two industry circuits. In all but one case, the UST algorithm uses less wirelength when compared to the Greedy-BST/DME [CoKo95, HuKT95] and BB+DME algorithms =-=[ChHH92b]-=-. For each circuit, the skew bound for BST construction [CoKo95, HuKT95] is set to be the smallest skew bound of all sink pairs. To compare the impact of a UST on power dissipation, [XiDa96] also perf... |

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Citation Context ...) Embedding of abstract topology, (iii) Planar routing, (iv) Buffer and wire sizing, (v) Non-tree clock routing, and (vi) Clock schedule optimization. Many results in (i)--(iii) were also surveyed in =-=[KaRo94]-=-. While we aim to cover all recent works on interconnect design and optimization in high performance clock routing in this section, this is not a comprehensive survey on clock synthesis and we left ou... |

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Citation Context ...ith low average wire length and bounded path length, pathological cases exist where the tree cost is not bounded. In order to compute a spanning tree with bounded radius and bounded cost, Cong et al. =-=[58]-=- extended the shallow-light tree construction by Awerbuch el al. [59], which was originally designed for communications protocols. The algorithm of [59] constructs spanning trees which have bounded pe... |

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Citation Context ...he target sink. The target sink was selected to minimize the distance between the sink and the partial tree. The algorithm uses the A* search technique, with delay calculated by a method described in =-=[Sa83]-=-. In [HoXK93], Hong et al. propose two tree construction methods. The first, called the Iterative Dreyfus-Wagner (IDW) Steiner tree algorithm. This method modifies the optimal Steiner tree constructio... |

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Citation Context ...rconnect line, respectively, and R0 and Co the driver resistance and the input capacitance of the minimum-size inverter, respectively. A polynomial-time dynamic programming algorithm was presented in =-=[107]-=- to find the optimal buffer placement and sizing br RC trees under the Elmore delay model. The formulation assumes that the possible buffer positions (called legal positions), possible buffer sizes, a... |

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Citation Context ... driver delay model precharactefizes the driver delay of each type of gate/buffer in terms of the input transition time 4, and the total load capacitance CL in the following forms of k/ctor equations =-=[34, 38]-=-: t01' (kl d- k2CL)4 +k3C --k4C I +ks, where k...s and k(... s are determined based on detailed circuit simulation (e.g. using SPICE [13]) and linear regression or least-squares fits. Similar k-hctor ... |

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Citation Context ...bjectives are constructions which provide shortest paths from the source to sink nodes. While this clearly minimizes path resistances, we also want to minimize the total tree capacitance. Cong et al. =-=[41]-=- showed that a minimum-cost shortest path tree is very useful for delay minimization. Given a routing tree T, they decomposed the upper bound signal delay tp at any node in T under the Rubinstein et a... |

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Citation Context ...le, Figure 25(a) plots HSPICE delay skew against pathlength delay skew for routing trees generated by the Greedy-BST/DME algorithm under pathlength delay [CoKo95, HuKT95] on MCNC benchmark circuit r3 =-=[Ts91]-=-. Not only is the correlation poor, but the pathlength-based BST solutions simply cannot meet tight skew bounds (of 100ps or less). On the other hand, Figure 25(b) demonstrates the accuracy and fideli... |

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Citation Context ... tree cost is not bounded. In order to compute a spanning tree with bounded radius and bounded cost, Cong et al.[CoKR92] extended the shallow-light 22 tree construction by Awerbuch, Baratz, and Peleg =-=[AwBP90]-=-, which was originally designed for communications protocols. The algorithm of [AwBP90] constructs spanning trees which have bounded performance for both total tree length and also maximum diameter. T... |

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Citation Context ...elay also has the maximum skew, minimization of the maximum delay also minimizes the maximum skew. 4.4.2 Simultaneous Tree Construction, Buffer Insertion and Wiresizing Most recently, Okamoto and Cong=-=[OkCo96b]-=- study the simultaneous tree construction, buffer insertion and wiresizing problem 10 . The following techniques are combined to develop a wiresized buffered A-tree (WBA-tree) algorithm: the A-tree al... |

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Citation Context ...erconnect tree as an RC tree: (a) an interconnect tree, (b) each edge is modeled as a n-type circuit, and (c) each edge is modeled as an RC line. w,, and the parasitics of the interconnect as follows =-=[7, 8]-=-: t(so, si)sr,(c,,/'2 + Cap(v)) e CPath( , s ) Z 2 ,,, GPath(,0,3, ) 2 e, GPath(.%,s, ) 147e, le,,I e, C Path(so. s, ) e,, Des(e, ) le41e,,I le,-I +rcrs-- +r Zsc,--, (3) ersPath(,s',us.. ) e,,&l)esle,... |

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Citation Context ...ing of Abstract Topology Given a prescribed abstract topology, the Deferred-Merge Embedding (DME) algorithm, proposed independently by Edahiro [Ed91], Chao, Hsu, and Ho [ChHH92a], and Boese and Kahng =-=[BoKa92]-=-, achieves exact zero skew for both pathlength and Elmore delay models. The enabling concept is that of a merging segment. The problem of bounded-skew embedding was first addressed independently by Co... |

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Citation Context ...RT constructions were very close to those of BB-SORT constructions. For random problems with 9 points, using 0.5 },t CMOS IC parameters, the SERT delays were only 3.9% above those of BB-SORT [10]. In =-=[72]-=-, it was also shown that the trees constructed using the Elmore delay model as an objective provided good performance under SPICE simulation. The authors enumerated all possible topologies for small n... |

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Citation Context ...f routing alternatively between the horizontal and vertical directions, the MMM method is also extended to allow one level of "look-ahead" to determine the more favorable direction. Chao, Hs=-=u, and Ho [ChHH92a]-=- presented another top-down topology generation approach called the Balanced Bipartition (BB) method. The heuristic divides the sink set recursively into two partitions with nearly equal total loading... |

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Citation Context ...ivision. In addition to replacing the GWSA algorithm in both the single-source and multi-source wire-sizing problems, the BWSA algorithm can be used in the simultaneous driver and wire-sizing problem =-=[8]-=- to be presented in Section 4.3.1. 4.2.1.4. Continuous and non-untform wire-sizing jbr single-source RC tree Another alternative to achieve non-uniform wire width within a segment is the optimal wire-... |

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Citation Context ...vely high for large clock nets, impacting circuit area, power consumption, and clock rates for large circuits. The Method of Means and Medians (MMM) algorithm proposed by Jackson, Srinivasan, and Kuh =-=[JaSK90]-=- generalizes the H-tree algorithm; the idea is to perform partitioning along x and y directions alternatively. Given a set of sinks S = fs 1 ; s 2 ; \Delta \Delta \Delta ; s n g to be partitioned, the... |

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Citation Context ...edding (DME) algorithm by [BoKa92, ChHH92a, Ed91] can be either applied to a given clock topology or combined with a clock topology generation algorithm to achieve zero skew with a smaller wirelength =-=[Ed93a]-=-. The methods in [CoKo95, HuKT95, CoKK95] address the bounded-skew tree (BST) construction problem under the pathlength and Elmore delay models by extending the DME algorithm for zero-skew tree to BST... |

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Citation Context ...to the heuristic of [64], described in Section 3.2.2. Afterwards, a post-processing procedure is applied to perform heuristic local optimization to further minimize the delay. Recently, Lillis et al. =-=[74]-=- addressed performance driven interconnect topology problem through the construction of Permutation-constrained Routing Trees or P-Trees. Their algorithm first constructs a MST for the point set, and ... |

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Citation Context ...tation is O(n3), while a naive approach may be O(nS); this may make it impractical for problems with large numbers of vertices. The third approach we discuss is an MST-based heuristic by Borah et al. =-=[55]-=-. It produces results that are comparable to the 1-Steiner algorithm, but with a complexity of only O(n:). Rather than optimizing a MST by merging edges, their method improves an initial MST by findin... |