Verification of timed systems using POSETS

Verification of timed systems using POSETS (1998)

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by Wendy Belluomini , Chris J. Myers

Venue:	In International Conference on Computer Aided Verification
Citations:	31 - 7 self

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@INPROCEEDINGS{Belluomini98verificationof,
    author = {Wendy Belluomini and Chris J. Myers},
    title = {Verification of timed systems using POSETS},
    booktitle = {In International Conference on Computer Aided Verification},
    year = {1998},
    pages = {403--415},
    publisher = {Springer-Verlag}
}

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Abstract

Abstract. This paper presents a new algorithm for efficiently verifying timed systems. The new algorithm represents timing information using geometric regions and explores the timed state space by considering partially ordered sets of events rather than linear sequences. This approach avoids the explosion of timed states typical of highly concurrent systems by dramatically reducing the ratio of timed states to untimed states in a system. A general class of timed systems which include both event and level causality can be specified and verified. This algorithm is applied to several recent timed benchmarks showing orders of magnitude improvement in runtime and memory usage. 1

Citations

243	A stubborn attack on state explosion - Valmari - 1992
208	M.: Modeling and verification of time dependent systems using time petri nets - Berthomieu, Diaz - 1991
195	Timing assumptions and verification of finite-state concurrent systems - Dill
136	Using unfoldings to avoid the state explosion problem in the verification of asynchronous 1: Comparison of the new algorithm with dynamic partial-order reduction Unfolding DPOR jCUTE number of paths time (seconds) size number of paths time (seconds) paths - McMillan
133	Using partial orders to improve automatic verification methods - Godefroid
83	Techniques for Automatic Verification of Real-Time Systems - Alur - 1991
78	Recoverability of Communication Protocols - Merlin, Farber - 1976
42	Efficient verification of parallel real-time systems - Yoneda, Schlingloff - 1997
42	Computer-Aided Synthesis and Verification of Gate-Level Timed Circuits - Myers - 1995
40	Some progress in the symbolic verification of timed automata - Bozga, Maler, et al. - 1997
38	Timing analysis in COSPAN - Alur, Kurshan - 1996
23	Finite-state analysis of asynchronous circuits with bounded temporal uncertainty - Lewis - 1989
23	STARI: A Technique for HighBandwidth Communication - Greenstreet - 1993
21	Representing and Modeling Circuits - Rokicki - 1993
19	Automatic synthesis of gate-level timed circuits with choice - Myers, Rokicki, et al. - 1995
17	Efficient timing analysis algorithms for timed state space exploration - Belluomini, Myers - 1997
16	Automatic verificaton of timed circuits - Rokicki, Myers - 1994
13	Modeling timing assumptions with trace theory - Burch - 1989
9	Verification of asynchronous circuits using time Petri-net unfolding - Semenov, Yakovlev - 1996
9	Timed event-level structures - Belluomini, Myers - 1997
5	Stari: Skew tolerant communication. unpublished manuscript - Greenstreet - 1997
5	Stari: A case study in compositional and heirarchical timing verification - Tasiran, Brayton - 1997
3	Implicit methods for timed circuit synthesis - Thacker - 1998
2	Practical applications of an efficient time seperation of events algorithm - Hulgaard, Burns, et al. - 1993
1	Efficient parial enumeration for timing analysis of asynchronous systems - Verlind, Jong, et al. - 1996